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Original question:

TLK2711-SP: Serdes transceiver with serial input (Similar to TLK2711)

TLK2711-SP: Clock input to TLK2711

R & D
Intellectual 560 points
Part Number: TLK2711-SP
Other Parts Discussed in Thread: CDCM7005-SP

Hello, 

I am using TLK2711-sp, with an FPGA. The clock to the IC is given by the FPGA board it self. FPGA is Xilinx Kintex 7. Could you please help me out, if i can directly feed the clock from FPGA to the TLK2711, or do i need to add any jitter reduction IC or something like it. If yes then please suggest one.

Regards

Bhrugesh

  • 0
    TI__Guru 62930 points
    Bhrugesh, You are likely correct. I am not familiar with the Kintex 7's clock jitter properties.
    However, the clock coming into the TLK2711 needs to have pk-pk jitter properties of less than 40ps. This is a little conservative, as it is frequency dependent. See this link for a few more details. e2e.ti.com/.../412382

    If your clock from FPGA cannot meet these requirements, and you need a -SP grade solution, there is the CDCM7005-SP. The CDCM7005-SP is is clock synthesizer/jitter cleaner. It uses a VCXO to create a clean clock. The FPGA can provide a dirty reference clock at frequency, or divided down.

    If this answers your question, please click "Verify it as the answer"
    Regards,
    Wade