Due to the U.S. Thanksgiving holiday, please expect delayed responses during the week of 11/22.

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74LVC8T245: SN74LVC8T245 Glitchfree Power-Up

Part Number: SN74LVC8T245
Other Parts Discussed in Thread: SN74LXC8T245

Hello,

A question regarding the SN74LVC8T245 dual-supply level translator.

I have read some of the former entries on this topic but would like to ask this nonetheless.

Following scenario:
- Port B = 5V (I/O side), Port A = 3.3V (FPGA side)
- 5V ramps up first, 3.3V is generated from the 5V and follows shortly after
- Operating Direction is fix A-to-B (DIR = H)
- We don't want any glitches to be driven on Port B durcing power-up

DIR = H means A-to-B, DIR = L means B-to-A

OE# has a pull-up to the 3.3V supply (later controlled/enabled via FPGA I/O).

How to ensure that we do not see any output glitches on the I/O side (Port B) during power-up?
The device has a feature to have all outputs in high-impedance state while any of the power supplies is low (say < 0.4V).
But what about the 3.3V power supply ramp-up phase (3.3V supply ramp in the range 0.8V ... 2.0V).
If we would have a simple pull-up to 3.3V on DIR as well,
wouldn't there be a chance for a short glitch on the B-Port output, e.g. when the acutal OE# switching level (disable level) is at 1.8V while the actual DIR switching level is at 1.2V?
Wouldn't it be safer (for this case) to have a pull-down on DIR (later switched to H via FPGA I/O) (FPGA I/O is High-Z during power-up and for some time afterwards),
so that any potential driven output glitch during the 3.3V supply up-ramp (because OE# level is not quite ready to disable) would be directed towards the FPGA I/O (instead towards the card I/O)?

Thanks