Hi TI,
I am a signal integrity engineer and am looking for some kind of information on acceptable dynamic under/overshoot.
This is typically specified as a maximum value above the DC static recommended input value (or below if it is a dynamic undershoot specification) and an acceptable time period or percentage of time for a given clock cycle to be over the DC recommended operating voltage (or an area under a curve of the overshoot voltage above recommended DC value).
If I remember correctly the 8T245 has no power clamp diodes and the max. voltage is pretty high so overshoot is not presenting a problem.
There are ground clamp diodes however and this is where I could use some guidance. It's obviously safest to design to the DC value (typically +/- 0.3V) and if this were a design at the beginning of the cycle I'd do this but the design I am checking is already well along in routing and I don't want to tell them to add a hundred or more series termination resistors.
I know this is not an easy number to come up with which is why it is not in the datasheet but any rough guidance that you could provide would be greatly appreciated.
Thanks Very Much TI,
Ned