I have a customer who is looking to do the following: utilize voltage isolation in such a way to power the cpu driving the data bus and address bus without powering the SD Ram and USB. Note that he does not want to change clock domains or data rates. So the idea is to be invisible during normal operation.
This brings the SN74CB3T16211 device into view. A bi directional level translator which could either be powered from two different 3.3v power supplies as long as the direction pin was automatic or a single power rail where we could simply tri-state the outputs.
1) Can we power the SN74CB3T16211 by 5V on the VCC if I only expect 3.3V to pass thru? This will allow more bias on the internal FETS and hopefully turn them on more.
2) What is the expected leakage thru the IO pins with the /OE pin de-asserted? (ie if the IO was at 3.3v, the other side was grounded and the output enable was high)
3) I need an IBIS model for the SN74CB3T16211, including a way to simulate the bus while the fet is on in hyperlynx.
4) If you have any other suggestion I will need IBIS models for them also
Thanks for your help.
