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SN74LVC3GU04: Matching for current mirror

Alfred Fuchs1
Intellectual 320 points
Part Number: SN74LVC3GU04
Other Parts Discussed in Thread: LSF0108, SN74AHCU04, SN74LVU04A, SN74HCU04

Note: This is in the logic forum, but the question is actually about linear use of  unbuffered inverters.

I have a situation where I want to do some rapid analog calculation (adding/subtracting) of a signal which is encoded as a current by using current mirrors at PCB-level.

For a 1:1 current mirror there are plenty of transistor pairs available, p as well as n, bipolar as well as MOSFET.

Actually I hit on the idea of using an LVC2GU04 or an AUP2GU04 (dual unbuffered!) where vcc or gnd is nc and only one halve of the totempoles is used.

I wondered if there can be an unintended artefact by not having power fully connected (bulk bias or so), but initial measurements show that the current mirror works reasonably as intended.

For a 1:2 current mirror, needed for more complex arithmetic, the situation is different.

There are very few transistor arrays supporting that and they tend to be pretty expensive.

So I think about using the 74LVC3GU04, one FET for input, two FETs connected in parallel for 2x-output, again with either Vcc or gnd unconnected.

(BTW: TI, pls make a 74AUP3GU04!)

I will test the setup anyway, but I may find some additional views by asking here.

Particularly: Is it justified to assume that those three FETs are matched (geometrically) to begin with?

Same electrical and timing parameters would indicate that probably they are, but there is not really a specification about matching in the datasheets.

The rule that outputs may be connected for parallel use would indicate that delays are well matched and therefore the I/O-curves too.

But in logic chips we pay less attention to crosstalk between channels which may matter in linear use (or may not).

Verifying such a use in an experimental setup would not rule out that there is a hidden weakness with the approach.

Is there?

  • 0
    TI__Guru* 96591 points

    Hi Alfred,

    That's a very interesting (and smart) use of logic.

    To get the obvious out of the way first - this is outside the datasheet spec and TI can't guarantee operation beyond the datasheet specifications. Also, I can't post our IP on the web, so what I say below is based entirely on publicly available information / things you'd learn in a basic process or VLSI design course in college.

    That being said...

    You can definitely expect that the FETs will be matched in this device (or any similar unbuffered inverter) - they are built on one monolithic IC, all instances come from the same design schematic, and are most likely geometrically identical, with some minor wiring differences.

    If you're using the nFETs, then leaving the VCC floating shouldn't impact operation -- the body bias comes from the ground connection.

    With the pFETs, I'd expect a similar situation, with the body bias coming from the supply pin. The floating ground shouldn't affect the pFET operation.

    You could connect the opposite supply pin to the same value that you are using, just to ensure that there aren't any floating nodes in the device. I would expect the opposite devices to remain in cutoff and not impact the operation much - leakage should be very minimal from those.

    You should note that there is an ESD protection circuit on the I/O pins that could eat some of your current, and that has some temperature dependence to it (generally speaking, more temp = more leakage).

    Also, I would recommend you take a look at a few other devices:

    LSF0108 - contains 9 n-channel FETs that share a gate connection.

    SN74LVU04A, SN74HCU04, SN74AHCU04 all include 6 channels of unbuffered inverters, which should also work for your described application.

    -

    I'll ask our systems team to consider the SN74AUP3GU04, but I can tell you that our plans are fairly set for the next few years, so you'll definitely want to use an existing solution for now.