Other Parts Discussed in Thread: LSF0108, SN74AHCU04, SN74LVU04A, SN74HCU04
Note: This is in the logic forum, but the question is actually about linear use of unbuffered inverters.
I have a situation where I want to do some rapid analog calculation (adding/subtracting) of a signal which is encoded as a current by using current mirrors at PCB-level.
For a 1:1 current mirror there are plenty of transistor pairs available, p as well as n, bipolar as well as MOSFET.
Actually I hit on the idea of using an LVC2GU04 or an AUP2GU04 (dual unbuffered!) where vcc or gnd is nc and only one halve of the totempoles is used.
I wondered if there can be an unintended artefact by not having power fully connected (bulk bias or so), but initial measurements show that the current mirror works reasonably as intended.
For a 1:2 current mirror, needed for more complex arithmetic, the situation is different.
There are very few transistor arrays supporting that and they tend to be pretty expensive.
So I think about using the 74LVC3GU04, one FET for input, two FETs connected in parallel for 2x-output, again with either Vcc or gnd unconnected.
(BTW: TI, pls make a 74AUP3GU04!)
I will test the setup anyway, but I may find some additional views by asking here.
Particularly: Is it justified to assume that those three FETs are matched (geometrically) to begin with?
Same electrical and timing parameters would indicate that probably they are, but there is not really a specification about matching in the datasheets.
The rule that outputs may be connected for parallel use would indicate that delays are well matched and therefore the I/O-curves too.
But in logic chips we pay less attention to crosstalk between channels which may matter in linear use (or may not).
Verifying such a use in an experimental setup would not rule out that there is a hidden weakness with the approach.