SN74LVC3G34: Seek SGPIO buffer

Hi team,

I  just check the SGPIO protocol,  the clock frequency is 100k max;

And SGPIO signal trans to backplane board and analyzed by CPLD and then lights up the hard disk LED indicator;

And I want to find a 3.3V Vcc, OD output, 4-ch with one OE pin, please help me check , thanks.

Best regards,

Andy Liu

Hi Ladisch,

Why do we need to use OR gate? I am confused, can you explain, thank you; 

Customers just want to control these 4 channels at the same time, can we use one OE letter to connect to our 4 OE pins at the same time to achieve this function?

And I find sn74alvc126 and sn74ahc126 are all 4-ch buffer with OD output, can they use at this circuit? 

In fact, the output of the buffer is connected to the CPLD, and then the output of the CPLD drives the LED light, and the output of the buffer does not need to directly drive the LED.

In fact, I didn't find the appropriate SGPIO protocol information, I'm not sure if our device can support SGPIO, please help to confirm, thank you

Best regards,

Andy Liu

The 74xx126 buffers do not have open-drain outputs.

Please specify what the output should be for all four combinations of data and OE.

Hi Ladisch,

Thanks for your comments, and I have know why you recommend OR gates (SN74LVC32A) in front of open-drain buffers (SN74LVC07A);

So our buffer SN74LVC07A can support  SFF-8485 Specification for Serial GPIO (SGPIO) Bus?

And I will communicate with customer for deep information about the logical relationship between the four outputs and OE, and tell you tomorrow, thanks.

Best regards,

Andy Liu