Other Parts Discussed in Thread: 2N7001T, SN74AXC1T45
Dear team,
We plan to add level shift function at TI clock gen output to translate voltage level from 1.8V to 3.3V. (CMOS/ single-end type)
However, the output voltage will up to 2.1V at clock gen output.
My question is,
Is there any risk if we connect Vref_A to 1.8V of LSF but the input signal voltage level up to 2.1V? (input signal voltage not the same as Vref_A).
Thanks,
Ben