Hi,
I'm trying to correlate the delay thru the LSF0101 part with the setup as in the datasheet using the IBIS model. I have 2 questions regarding it. I'm not seeing exactly the same results as in the datasheet.
1. The out to in delay comes out be ~0.7ns. Datasheet has 1ns listed
2. The out signal does not reach 3.3 with the test setup.
Below are snapshots from the ADS setup. Can you see if anything needs to be changed to correlate to datasheet results.
Thanks.
Datasheet output
Hi Nikhil,
I am not sure I understand your concern as 0.7ns should be better than 1ns (and with a difference of just 0.3ns). However, please note that the IBIS models are not designed to verify delay as they are mainly used for signal integrity.
The device is also a passive switch; without any buffered I/Os to be modelled with IBIS with the VrefA/VrefB pins connected directly to the source/drain of the internal FET (shown below) operating similar to analog behaviors with the IBIS model operating just like a switch. Hence, the model cannot translate 1.8V input to a 3.3V output for example as it can only do the same voltage translation. (See [FAQ] How do I Approximate Propagation Delay and Channel to Channel Skew in an Analog Switch/Multiplexer?).
Your case will also not likely match the test conditions similar to the datasheet output you provided (for an ideal situation) which would have system to system variations and would further suggest using the LSF EVM to test and verify the signal integrity as well as the delay. Also see [FAQ] How do the LSF translators work?, thanks.
Best Regards,
Michael.
Hi Michael,
Thanks for the update. I was trying to estimate what the max delay thru the switch will be as the datasheet only lists the "Typ" values. I agree, IBIS sim is not the best approach for this. Can you provide a SPICE model for the buffer.
I read the info you provided on how to approximate prop delay and my delay comes out to be close to the Typ value listed below.
