Our test shows that the transmission input delay is about 1.6uS, which is very different from the tPHL parameter in the data manual. What is the cause of this, or is this the case with this model of tPHL?
Our product needs an AND gate with both tPHL and tPLH within 300ns. Is there a P2P compatible solution recommended?
There are two signals in the picture, one is input signal A and the other is output signal Y.
Hi HY,
The input needs to be driven below V_IL (0.8V) to be a valid low-state input. Your input signal is not transitioning to a LOW state until 1.6us, which is very different from the device not having the correct delay. You need to fix the input signal.
The device you are using has reduced input thresholds to support backwards compatibility with TTL logic. You could easily swap out to using a normal CMOS device such as SN74HCS08, SN74AHC08, or SN74AC08 -- however these will not necessarily fix the issue (that input is very bad for a logic device) - you really should fix the input signal.
