Hi
I know floating levels (HighZ) at a CMOS gate input is a dangerous problem as both FETs can be ON simultaneously, thus to create a short from Vcc to GND and burn this gate.
I would like to ask the following:
1. If the OEn (output enable) pin of the 74lvc16245ADGG device is at "1" (output at HighZ) , will it change in any matter the above danger to the chip due to floating inputs?
2. If I don't want to change the current PCB layout and had pull ups at the chip inputs, what are my other options to reduce the above risks?
3. Is the 74lvcH16245ADGG a good option to overcome the floating inputs state?
4. In case I replace current chip with the 74lvcH16245ADGG chip, does it mean I have to remove from my current design all the pull ups over the 74lvcH16245ADGG outputs?
Looking forward to hear from you
Thanks
Ami