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Hi,
I am using SN74LV08 in a design as follows
Kindly note that U15.PBRST is an input having internal PU of 40K to 5V rail.
Initially, 5V rail is powered, but 3.3V comes after a 10sec. delay. During this time, I am seeing a 0.6V at U14 pin#6 (output of AND gate). instead of expected 3.3V.
Kindly let me know the fault with this circuit?
Regards,
Thomas Joseph
Hi Thomas,
Could you probe that node with a multimeter to find the resistance between that node to VCC and GND and post the results? Also, do you have a board layout that you could post for this?
Also, do any of the other AND gates have unexpected outputs during this time?
Best,
Ian