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CD4044B-MIL: Logic Dominated by R=0

Part Number: CD4044B-MIL

I am looking for guidance on when this SR latch is in the 'forbidden' state with S and R both set to 0 what the logic output is; the data sheet has a note saying this output is dominated by R = 0, but no state table to show the transition conditions when both S and R are set to 0. In my application I am looking for if S has been set to 0 for a while and if R is then transitioned from 0 to 1, does the output follow R and go low?