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SN74AXC4T774-Q1: SN74AXC4T774-Q1 is Driving MISO line to LOW

Part Number: SN74AXC4T774-Q1
Other Parts Discussed in Thread: SN74LVC1G125

Hi,

SPI devices configured in the device as shown below. MISO line is output from Level shifter.

When SPI slave-2 driving MISO line, working as expected.

When SPI slave-2 driving MISO line, MISO signal going upto 0.4V only(IO logic is 1.8V). SPI salve-2 can't drive MISO line to HIGH. Level shifter strongly driving the MISO line to "LOW".

When isolated Level shifter from the SPI bus, SPI slave-2 MISO line working as expected(1.8V level).

Does this expected behaviour when using SN74AXC4T774-Q1 ?

  • The problem is that the MISO output of the level shifter is always active.

    To disable all the level shifter's outputs when slave 1 is not being addressed, connect its /CS to the level shifter's /OE. (Ensure that you have pull-up or -down resistors near slave 1 to prevent the lines from floating.)

  • Disabling the Level shifter output is the easiest way to solve the issue. 

    SPI is multi slave topology, above scenario of SPI slave connection is normal. My question is does this expected behavior of SN74AXC4T774-Q1? 

    Also, any other way to control strong driving capability of Level shifter without effecting signal quality?

  • The outputs stay enabled as long as /OE is low. This is expected.

    If you do not want to disable all outputs, you can insert a three-state buffer (e.g., SN74LVC1G125) after the level shifter's output. But you cannot fix this without changing the board.