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LSF0204-Q1: Leakage Voltage in VREFA from VREFB

Part Number: LSF0204-Q1

Hi TI Team,

We are using LSF0204-Q in our circuit for level translating the 1.8V signal to 3.3V signal. The 1.8V supply is from a LDO and it is connected to the VREFA and 3.3V supply is connected to the VREFB. There is a pull-up resistor of 2.2KOhm at VREFA side and 1K at VREFB.

We are facing some issues when the 1.8V LDO is turned OFF. The expected voltage is nearly 0V at the 1.8V LDO output, but we are getting around 0.6V~0.7V here. While observing we came to know that this voltage is coming from the level translator. Please confirm whether this is an expected behaviour. During this state, VREFA (1.8V) is OFF (we are observing 0.7V)and VREFB (3.3V) is present. 

Thanking you in advance.

Hemanth

  • Hey Hemanth, 

    During normal translation operation with EN biased, a small leakage current will flow from VREFB to VREFA and will be limited by the internal 200kohm internal pullup. Could you confirm if the EN pin was still powered up in your test? 

    Its important to also note that not all power supplies can sink in the back current from VREFB to VREFA, such as LDOs. This in turn, will cause VREFA to actually float up above the desired levels. For further clarification, please see Understanding the Bias Circuit for the LSF Family.

    Regards,

    Jack 

  • Hi Jack,

    Thanks for the reply.

    During the test case the EN pin is HIGH, VREFB is 3.3V and VREFB is supposed to be 0V but reading as 0.6V~0.7V. Even though this is a bi-directional device for this particular application we are using this to translate data from Device 1 (operating at 1.8V) to Device 2 (operating at 3.3V)

    In A1, A2, A3 we are reading 0.7V, 0.7V, 0.2V even though the Device 1 connected at this signals is powered OFF and not sending any data.

    In B1, B2, B3 we are reading 3.3V, 3.3V, 0.4V. The Device 2 connected at this side is ON and it is reading it as a  wrong 110 (3.3V, 3.3V, 0.4V) state. The expected state when Device 1 is OFF is 000.

      

  • When EN is high, the two sides are connected (both the I/O channels and the VREF pins). To isolate the two sides from each other, you must pull EN low.