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SN74LVC8T245-Q1: SN74LVC8T245 Conditions that translation direction swaps?

D J
Prodigy 110 points
Part Number: SN74LVC8T245-Q1

Hello,

Are you aware of any conditions such as supply noise or brownout condition that would cause the direction to swap from B->A to A->B erroneously given below schem?

Decaps are of course, placed close to device and solid ground pour is used.


Best

dimitri

  • +1
    TI__Guru 51106 points

    Hi Dimitri,

    Yes, noise or burnout issue could lead to faulty conditions on OE or DIR for directional changes i.e for example, a short to VCC on DIR may cause direction to swap from B->A to A->B erroneously. Additionally, a slow / floating input or noisy input may also cause DIR to pick up a high instead of low for A->B.

    You may further confirm if any damages, i.e if issue is consistent with all other units / just 1 unit or if related to system environment, thanks.

    Best Regards,

    Michael.

  • 0 in reply to Michael Ikwuyum
    Prodigy 110 points

    Thank you Michael,



    In this case, OE and DIR are both shorted to GND with copper so i would be surprised if they could float.



    Michael Ikwuyum said:
    Additionally, a slow / floating input or noisy input may also cause DIR to pick up a high instead of low for A->B.

    So for Slow inputs, what is the mechanism that would cause DIR to pick up HIGH? I would think that a Fast / sharp transient would be what would couple to DIR.

    And could you recommend any mitigation for this case? E.g. RC Filter, 10k pulldowns on each pin, small cap like 100pF/220pF to ground? PWM frequency is only 500Hz so there is not any issue with attentuation.

    Best

    Dimitri

  • +1 in reply to D J
    TI__Guru 51106 points

    Hi Dimitri,

    D J said:
    So for Slow inputs, what is the mechanism that would cause DIR to pick up HIGH? I would think that a Fast / sharp transient would be what would couple to DIR.

    Please help see [FAQ] How does a slow or floating input affect a CMOS device? to help confirm if the expected waveforms for LOW observes similarities with the oscillation for HIGH as well i.e do you observe noise around 1/2 Vcc?

    D J said:
    And could you recommend any mitigation for this case? E.g. RC Filter, 10k pulldowns on each pin, small cap like 100pF/220pF to ground? PWM frequency is only 500Hz so there is not any issue with attentuation.
    • The recommendation would be to ensure faster than 5ns/V for 5V inputs.
    • Remove filters as they tend to slow down the transition as well. May use pulldowns if floating.
    • Use decaps on power supplies dependent on noise levels i.e more if still noisy.

    If specific recommendation is needed, please further help clarify which case is precisely the concern i.e noise, slow / floating inputs, shorts or damages, etc, thanks.

    Best Regards,

    Michael.

  • 0 in reply to Michael Ikwuyum
    Prodigy 110 points
    Michael Ikwuyum said:
    Please help see [FAQ] How does a slow or floating input affect a CMOS device? to help confirm if the expected waveforms for LOW observes similarities with the oscillation for HIGH as well i.e do you observe noise around 1/2 Vcc?

    Oh i see the concept , may be solved with schmitt trigger

    thanks for the help, i will ask any further questions if i receive more info