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LSF0108-Q1: Design Support

Part Number: LSF0108-Q1
Other Parts Discussed in Thread: LSF0108

Hello Team,

We need some design support regarding the LSF0108 voltage translator. We have used this IC in our design for UART application. We planned to use this IC only to protect the input UART signal in case 5V TTL is connected at the B end. We don't need up-level shifting. But we missed to add the recommended pull-up 200K resistor for EN and Ref B. The communication is working fine without any issues. We only see the level down to around 2.7V at the B channel instead of 3.3V. Will the direct connection of 3.3V to En and refb can damage the IC?  


I have attached the schematics image below. VDD_MCU is the output of 3.3V LDO and IO_A is another 3.3V LDO output. Both are 500mA LDO's.

  • The 200 kΩ resistor would require a voltage drop between RefA and RefB; it's not needed when both are the same. This will not damage the LSF.

    The LSF is a passive switch that allows low-level voltages through; high-level output voltages are generated only by the pull-up resistors.

  • Hey Danish, 

    It seems that you are using this device not as a translator, but more so to put the I/Os in HIGH-Z when desired. Because of this, the following guidelines won't directly apply:

    -VREFA must be at least 0.7V less then VREFB for best signal integrity- which holds true for when the LSF is being used in translation use cases 

    -EN pin and VREFB shorted together to bias/ regulate the gate of the FETS per channel- since the LSF is being used as a simple switch in your case, applying a bias directly to EN that is equal to VREFA and VREFB is OK

    However, you should still include a 200kohm pullup resistor on VREFB to limit the leakage current flowing through the internal FET of the LSF0108, as well as limiting the leakage current into VREFA (especially in cases where VREFA  VREFB). 

    You may also see The Logic Minute Videos for additional information. 

    Regards,

    Jack