TXB0108: TXB0108PWR Reading Wrong Data

Hi Arijeet,

Please help remove the pull-up and double check. See datasheet's section 8.3.4 for more information, thanks.

Best Regards,

Michael.

Hi Michael,

Which Pull up you are telling? 
My card is not plugged into the Backplane. The net only has a PD of 100k.

"I am facing an issue when the card is not plugged in the backplane, instead of reading 0 I am reading 1 from FPGA. When I checked with the multimeter I saw a logic high of 1.714V."

The TXB is not a buffer. And its pins cannot be configured as outputs or inputs; both are always active on both sides. To allow bidirectional transmission, its outputs have a very low drive strength and require the other devices to have a higher drive strength; this is the opposite of a buffer.

For unidirectional signals, use actual buffers, e.g., SN74xxx541. With a direction control signal, use transceivers, e.g., SN74xxx245.

It looks as if another device is pulling this line high. This might be a pin of another TXB.

The input or output is related to the pin configuration of fpga. 

I don't have any control of OE from FPGA. It is Pulled High with 1.8V, if you suggest i can add a capacitor to delay the rise time for the OE signal

Hi Clemens,

I am not sure who can drive, when card2 FPGA is configured in reception mode only

Hi Arijeet,

Could you confirm the 10 K pull-up is disconnected?

If so, card 1 of TXB seems to be outputting. However, you intend for a low on the outputs. Hence, can you further confirm the input of the TXB is also low as the device has internal 4 K that would have priority over the external 100 K  with inputs being high? Thanks.

Best Regards,

Michael.

Hi Michael,

Sorry, for some confusion.

I am seeing logic high on TXB output (in card 2), in this below situation, when card1 is unplugged(not present).

100 kΩ is not enough to override the TXB output.

The TXB cannot be used in this application.

Clemens, Any resistor value change will help?

No; the resistor is either too weak to affect the voltage, or too strong for the sense function.

You could redesign the circuit with a 0 Ω pull-up on card 1, but it would be a better idea to not use the TXB at all.

Hi Clemens, I have done a few modifications from the FPGA side, inside FPGA I have configured the input pins with internal PD. 
In this scenario, my card2 is only plugged to backplane.

But the issue remains the same, still I am reading 1 (1.314V) for few of the pins.

The TXB IC doesn't have any internal PU & I am not driving these pins as high, but how do I read the pin state as 1? Any clue on this?

Reg. the 100k PD, this value is recommend (>50K) in the TI document.

Hi Michael,
Please help me understand the internal structure of TXB, the 4k is in series with the internal buffers and the A side is PD (low) to 100k, so how on the B side I see 1 ?



Please correct me if my understanding is wrong as I am new to this.

Michael, what is the known state here for my case?

Thanks, Michael, any pin-compatible part we have?

Hi Michael, It seems I need to respin the card.

For the time being, I am proceeding with the below approach, I have connected 100k PD at the output side of the TXB IC which is connecting my FPGA in card 2. so there is no dependency on the TXB IC for logic low. 

For logic high I will be driving that pin high from the card from card 1.

Hi Arijeet,

Please help share the results. However, note that the 100 K pull-down is still weaker than the 4K. Hence, the device would most likely overpower the 100K, thanks.

Best Regards,

Michael.

Sure, Michael, I need to check this setup. Once validated I will update you with the observation.