SN74AHCT541: while OE1 is high, OE2 is low, why output signal changes its state

The output should remain high impedance even if just one of the OE signals is kept high. You could try pulling OE2 high but in theory this should not change anything.

What is happening in the system that is causing the OE2 signal to go low suddenly?

Hi,

as i mentioned this is old design, OE2 going low for short moments is probably the way the code was written in the past.

We are in the process of getting it corrected, However I gave a try with pull up resistors of 4.7K ohms on both OE1 and OE2, but still I see similar behavior as above ?

I dont see any change with or without pull up resistors of 4.7K ohms, Is there any specific value that is suggested to check?

Like I mentioned I don't expect pull-up resistors on both OE to change anything. The output should be high impedance even if only OE1 is pulled up. 

The issue here is from the code causing OE2 to go low. That code is also influencing the output of the device, it very likely has nothing to do with the actual state of the OE2 pin. Does the change in OE2/whatever happens in the code coincide with some sort of significant EMI or switching event? Are these two signals somehow physically connected in a way that they would both be pulled low by whatever function is responsible in the code?

I could see that influencing the high impedance voltage on the output pin. 

The reason i mentioned about high impedance is : Datasheet refers specific to the pull up resistors to get high impedance.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Probably my following observation/issue is because we did not have a pull up resistor on OE1 and OE2, we do see momentary low at the output, when OE1 is high and OE2 is low for short duration.

Vinay, you also quoted this portion of the datasheet:

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide noninverted data when they are not in the high impedance state.

You also posted the truth table:

Note that, while OE1 is high, OE2 is don't care. Thus Y should be high impedance even if OE2 goes low at any point while OE1 is high.

I agree to the point you mentioned, but my concern is : unless we do have a pull up resistor on board for both OE's, do you think the device can provide high impedance state at all ?

Today I shorted OE1 and OE2 to MIDE_RD_IF7 pin, which is held high continuously and only made low for short duration at a rate of 1second.

CH1, CH2 are high, but still the output signal CH4 (green) does have this glitch for short duration.

Any comments about it? Image 1:

After shorting OE1 and OE2, one good response I see is, we do not see false output signal at CH4 during this instance as per Image 2.

Image 2:

But there are other instances where output still has glitches at certain instances at a rate of 1ms as shown in above image 1.

Yes, it should be able to even with only one pull-up

Any comments about Image 1 observation?

What is connected to the output of the device?

those outputs are connected to another SN74AHCT541 buffer itself.

Btw, both buffers are enabled at different times.

Atleast in the image 2 i shared in the last above images, where OE1 and OE2 of first buffer were shorted and only active at a rate of 1 second.

Vs

The second buffer is enabled at different rates (am guessing it is 1 milli second).

Is it possible that the first buffer is in tristate as both OE1 and OE2 are high and what would be the effect due to it as the second stage is just receiving?

Also I think to read correct data from the first buffer to second buffer output, I think both had to be enabled at same time, other wise the first buffer output might be in tristate while the second buffer is enabled?

vinay kattela said:

Also I think to read correct data from the first buffer to second buffer output, I think both had to be enabled at same time, other wise the first buffer output might be in tristate while the second buffer is enabled?

Yes, this is correct. All of the second buffers inputs are effectively floating when the first buffers outputs are high impedance at any point.

Also, I imagine what is happening causing the glitches is that the second buffer is being powered on and there is some sort of backdrive occurring on the high impedance outputs of the first device for a brief moment.

Hi Malcolm,

Thank you for taking time and reviewing datasets.

Today I tried with following setting.

First buffer OE1 and OE2 are ground, so the first buffer is ON continuously.  

While i dont have control of second buffer, because it is being controlled by the main processor, i just left it as is to reduce any other conflicts at system level, which would toggle at a rate of 1ms, sometime within that 1ms rate, there is continuous burst pulses too.

Per your last response about "sort of backdrive occurring on the high impedance outputs"  Even with first buffer ON continuously(as OE1 and OE2 are ground to enable) : I still see the MIDE 3 signal output of first buffer toggling and aligns with the ON/OFF rate of second buffer ?

Is there any specification on the rate at which we could turn ON and OFF the buffer ?

Based on datasheet information provided in switching characteristics, I see the max is 10ns, but in our use cases I dont think we switch that fast.

At times MIDE 3 signal output 

i.) does go only till 1.8V level (you can see it in IMAGE A)

ii.) at times it does go till 0V ( you can see it in IMAGE C )

For example : in the following image A,

CH1 is OE1, OE2 of first buffer connected to ground--> continuously ON(0V)

CH2 is MD-RD signal that enables 2nd buffer ON/OFF -> this signal switches at a rate of 1ms, with some burst pulses

CH3 is first buffer MIDE3 input, which is consistently high and no glitches

CH4 is the first buffer MIDE3 output, which does switch and aligns with MD-RD signal 

IMAGE A:

Another observation : Overall we are definitely making progress, but I want to have a clear reason for the behavior of this IC.

Scenario 1: With standard settings, which means

OE1 of first buffer switches at a rate of 1second, OE2 of first buffer switches at a rate of 1ms

CH1signal : Enable(OE1 and OE2) of second buffer switches at a rate of 1ms

CH2: MIDE D3 output from buffer 1 

When I turn ON our entire system, I see there are lot of burst pulses sent over CH1, in the scope capture you can see the initial period of 4.32 seconds we have lot of burst pulses which does have effect on first buffer MIDE3 signal, pulling it to 0V Vs later to 4.32 sec period...we can see the burst pulses run at a less rate on CH1.

IMAGE B:

Scenario 2: With modified settings, which means

OE1 and OE2 of first buffer connected to ground to enable it continuously, this is the only change done here

CH1 signal on scope : (OE1 and OE2) of second buffer switches at a rate of 1ms, not changes done here

CH2: MIDE D3 output from buffer 1 

When I turn ON our entire system, I see there are lot of burst pulses sent over CH1, in the scope capture you can see the initial period of 6.8 seconds we have lot of burst pulses which does have effect on first buffer MIDE3 signal, pulling it to around 2.4V Vs later to 6.8 sec period...we can see the burst pulses run at a less rate on CH1 and that's when we can see it does go low down to 0V.  

IMAGE C:

Comparing images of CH2 going low for long time is seen on Scenario 1, which can actually give a false alarm for MIDE3 signal.

I see it is improved if we short OE1, OE2 of buffer 1 to ground as captured in Scenario 2.

Overall  I see there is a limitation on switching ON and OFF the 2nd buffer, which I would like to understand what is the limitation of that switching, can this switching backdrive the buffer 1 outputs ?  Appreciate your review and feedback.

Here we are talking specifically about one output signal, am sure this could happen all across the outputs.

I hope am not confusing a lot with the datasets here, if required we can have a conference call to sort this out.

Thank you

This seems like poor/no decoupling on VCC pins.

Sure, I can give a try with a cap installed to check the response for this IC.

Meanwhile : Is there any specification on the rate at which we could turn ON and OFF the buffer ?

Based on datasheet information provided in switching characteristics, I see the max is 10ns, but in our use cases I dont think we switch that fast.

No, there is no such specification.