SN74LVC1G123: SN74LVC1G123 and the CD74HCT4538E: Recommendations to improve the design of highly reliable circuits using SN74LVC1G123 and CD74HCT4538E components.

Hi Slim,

The 51 Ohm resistor is important if you are using a poorly filtered power supply that would power down abruptly. This could cause the capacitor to rapidly discharge into the device. Otherwise, it is not necessary.

I'm not sure what you mean with question 2. That seems very specific. Could you share a schematic?

Best,

Ian

If we examen the CD74HCT4538 datasheet, especially Figure 2. It is evident that the external capacitor (Cext) is connected to pin 1 (15) and pin 2 (14) across the N channel MOSFET located between these pins. The Cext is also connected to Vcc through a P Mosfet.

Question:
Besides the abrupt Vcc power down being a potential occurrence to rapidly discharge the capacitor Cext, is it possible for the Cext to be rapidly charged through the PMosfet or quicky discharged trough the N Mosfet during a specific transition event?

I think that the N Mosfet and P Mosfet inside the CD74HCT4538 play a role in transferring a charging or discharging current from Cext during a specific transition event, so the 51 Ohms resistor in series with Cext is necessary to control the current flow. Can you please consult the engineer in charge for further guidance and clarification?

My question#2 is about an integrated circuit that includes a discharge pin, like the CMOS version of the 555 timer, as an example. The CMOS 555 timer has a pin 7 (Discharge) which allows for a discharge path for the timing capacitor through the N Mosfet inside the 555 timer. Do you think that a 51 ohm resistor would also be a good practice for such IC when the timing capacitance exceeds 0.1uF?

Kind regards
Slim

Hi Slim,

The FETs detect the charge level of the RC to control the internal logic of the monostable. They do not rapidly charge or discharge the capacitor, outside of abrupt VCC changes. The 51 ohm resistor is only necessary to control current flow in an abrupt power down situation.

For the 555 timer, I would defer to the layout recommendations in the datasheet of that device.

Best,

Ian

Based on the logic diagram shown in figure 2 of the CD74HCT4538 datasheet, the internal logic of the monostable controls the N channel and P channel mosfet to regulate the RC charge level, and not the opposite. Additionally, according to the logic diagram of figure 2, the N channel and P channel mosfet do not serve as a charge level detector.

I would appreciate it if an Integrated Circuit Design Engineer from TI could review my question and provide his explanation and recommendations to help me achieve a rugged design with the CD74HCT4538.