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TXV0106-Q1: Output channel to channel skew and duty cycle variation

Part Number: TXV0106-Q1

Tool/software:

Hello team:

I have some questions about the output channel-to-channel skew and duty cycle variation described in the datasheet:

1. How are these two parameters measured, and what methods are used to obtain the values provided in the datasheet?

2. When calculating the timing margin for RGMII, should these two parameters be added together?

3. Are there any reference documents for calculating the timing margin with level-shifting chips. 

Thank you and Best Regards.

  • Hi,

    1. Apply the same input signal simultaneously to all channels of the level shifter. Measure the propagation delay from the input to the output for each channel independently. This can be done using an oscilloscope, logic analyzer, or other appropriate test equipment. Calculate the difference between the longest propagation delay and the shortest propagation delay among all the channels. This difference is the channel to channel skew.
    For example, if channel 1 has a propagation delay of 5 ns, channel 2 has a propagation delay of 6 ns, and channel 3 has a propagation delay of 7 ns, then the channel to channel skew would be 7 ns - 5 ns = 2 ns.

    2. RGMII specs are stand alone standards for each parameter with no additions. 

    3. The timing specs are measured and validated for the chips and not calculated. Do you have a target spec of interest you would like to clarify if device can meet? You may also see the product folder with referenced documentation https://www.ti.com/product/TXV0106-Q1#tech-docs

    Best Regards,

    Michael. 

  • The channel-to-channel skew measure the difference in propagation delay between different channels.
    The duty cycle variation measures the difference in propagation delay between rising and falling edges on the same channel.

    Adding them would not make sense.
    The channel-to-channel skew is an error that can reduce the setup and hold times.
    The duty cycle distortion is an error that can increase/reduce the clock's duty cycle away from 50 %.