SN74LV123A: How to handle unused pins

Hiromu Susami

Prodigy 100 points

Part Number: SN74LV123A
Other Parts Discussed in Thread: SN74LVC1G123,

Tool/software:

Hi experts,

I want to know how to handle unused pins.

[Issues]

Connect Rext and Cext pins to GND -> abnormal heat generation

* Open Rext and Cext pins -> No abnormal heat generation

[Questions] The data sheet does not describe how to handle unused pins.

Q1. Please let me know how to handle unused pins.

Q2. Why should we do that? Please tell me the reasons clearly.

Best regards,

Hiromu Susami

1 month ago

0 Clemens Ladisch 1 month ago

Guru 262920 points

This is strange. I do not understand where a high current could flow. And letting the C_ext/R_ext pin float does not sound like a good idea.

Anyway, just use the SN74LVC1G123.

0 Hiromu Susami 1 month ago in reply to Clemens Ladisch

TI__Prodigy 100 points

Hi Clemens,

Thank you for suggesting another device. But since my customer plans to use SN74LV123A, we want to know what to do with this device.

Is there any other idea to solve this problem? Or, is there some information which I should ask customer?

By the way, the competition device (HD74LV123A) has the following description:

"The input pins for unused circuit should be used under conditions to fix the outputs to avoid malfunction cased by noises. Also, it's recommended that Rext / Cext terminals are open and external parts are not connected to."

https://www.renesas.com/jp/ja/document/dst/hd74lv123a-rej03d0314-0600z?language=en&r=527206　

0 Malcolm Lyn 30 days ago in reply to Hiromu Susami

TI__Genius 16660 points

Hi Hiromu,

Luckily we have internal schematics for the design of these devices. I've taken a look and I think it's fine to leave these pins floating.

Best,

Malcolm

0 Hiromu Susami 30 days ago in reply to Malcolm Lyn

TI__Prodigy 100 points

Hi Malcolm,

Thanks for the information. If possible, would you like to know why it's fine to leave these pins floating, do you have any information?

Best regards,

Hiromu

+1 Malcolm Lyn 30 days ago in reply to Hiromu Susami

TI__Genius 16660 points

Hi Hiromu,

These signals are not connected to CMOS gates, they are connected to the drain, so there are not the same concerns in regard to oscillation or unknown voltage levels.

Best,

Malcolm

0 Ryoma Ohashi 30 days ago in reply to Malcolm Lyn

TI__Expert 3020 points

Hi Malcom,

Do you have any idea on why a abnormal heat issue happened by connecting the Rext and Cext pins to GND?

Regards
Ohashi

0 Malcolm Lyn 30 days ago in reply to Ryoma Ohashi

TI__Genius 16660 points

Ohashi,

It looks like this would allow for possible connection from VCC to GND under certain conditions. I am not a design engineer so I cannot answer confidently.

Best,

Malcolm

0 Ryoma Ohashi 29 days ago in reply to Malcolm Lyn

TI__Expert 3020 points

Hi Malcolm,

My customer wants to double check the internal circuit.

In this app note, seems that there is only low side FET for Rext and Cext.

https://www.ti.com/jp/lit/an/slva720a/slva720a.pdf

But in the below FQA, seems that there is high side p-FET between Vcc and Rexc/Cext. Seems that this FET was causing the heat issue in some kind of situation.

https://e2e.ti.com/support/logic-group/logic/f/logic-forum/863529/faq-how-does-a-monostable-multivibrator-one-shot-work

Which configuration is correct?

Regards
Ohashi

0 Malcolm Lyn 29 days ago in reply to Ryoma Ohashi

TI__Genius 16660 points

Hi Ohashi,

The second configuration is correct (with high side PFET).

Best,

Malcolm

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SN74LV123A: How to handle unused pins