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TPLD1201: How to implement a 200ns delay for a 307kHz 50% DC 5V-logic input signal?

Part Number: TPLD1201

Tool/software:

My customer wants to have a 200ns delay of above mentioned input signal.

Is this possible to implement on TPLD1201 or TPLD0801?

Can you provide a demonstration file that showcases this for InterConnect Studio?

  • Hi Walter,

    The closest way to do this is just using the PFLT block in delay mode for a straight 250 ns delay as shown below

    250nsDelay.syscfg

    Regards,

    Owen

  • Hi Owen,

    I start to familiarize myself with the new TPLD devices and I built a test-file for different delay options.

    Your suggestion above seems to work in my file, but the other options with clocked delays do not produce any output in the simulation...

    What do I do wrong?

    Test-Delay.syscfg

    Best Regards,

    Walter

  • Hi Walter

    I also tried to use delay blocks to test this. The issue with doing that is as said in the datasheet there is a component of syncing with the onboard clock.

    In doing so I believe the delays are missing the timing of the signal and constantly being retriggered.

    In other words the delay is seeing a second rising edge before it has time to output it's first rising edge causing a retrigger in the macrocell. This would output a constant high as the delay block is constantly being held in the reset mode.

    Regards,

    Owen