Tool/software:
In the LVC Designers Guide, it states "A characteristic of all CMOS input structures is that any unused inputs should not be left floating; they should be tied high to VCC or low to GND via a resistor. The value of the resistor should be approximately 1 kΩ. If the inputs are not tied high or low
but are left floating, excessive output glitching or oscillations can result due to induced voltage transients on the parasitic lead inductance inherent to the device input and output structure."
Does this same guidance apply to AUP logic devices? The datasheet shows inputs for various logic configurations directly tied to Vcc or GND.
