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TXB0104-Q1: It was connecting to bootstrp pin and need to know it bootstrap level?

Alpha Ting
Intellectual 550 points
Part Number: TXB0104-Q1
Other Parts Discussed in Thread: TXU0204-Q1, TLV840-Q1

Tool/software:

Hi sir

The TXB0104-Q1 is connecting between SOC bootstrap pin and usb-to-uart bridge(FT230XQ-R).

The bootstrp pin side (point B) has pull low resistor 47Kohm and the other side is connecting to bridge RXD input (Point A). The RXD input has a pull up 40K~190Kohm.

I am asking when the TXB0104-Q1 OE is enabled, what is the Point A and Point B voltage at POR and DC stage.

My target is to have Point B LOW.

Please help me understand it.

  • 0
    Guru 317280 points

    These resistors violate the limit in section 8.3.5 of the datasheet. (And weaker resistors would be overriden by the TXB's outputs.) The resulting voltage is not specified.

    The TXB should not be used with pull-up/-down resistors.

    For unidirectional UART signals, use the TXU0204-Q1 instead.

  • 0 in reply to Clemens Ladisch
    Intellectual 550 points

    Hi Clemens

    (1) If I changed the point B to 100K pull low for SOC bootstrap required, is the point B voltage level 0V or 1.8V for DC stage?

    (2) if the pull low resistor impacted the output driver voltage by point B, can I use 1Kohm to strong pull low to set the output 1.8*(1/5)=0.36V for DC stage?

    (3) When system is normal boot, the port is configured to UART and drive level by SOC. The idea right?

    (4) It was because the board was gerber out, I need a workaround.

  • 0 in reply to Alpha Ting
    Guru 317280 points

    1. The voltage at point B is determined only by what the A2 pin outputs. This might be high or low.

    2. The TXB has a rated drive strength of 20 µA. Such a strong pull-down would force the signal to be always low.

    It is not possible to have a bootstrap pull-down with the TXB (or TXS). I would recommend to keep the TXS; it is more robust then the TXB. The simplest way to force the signal low during power-up might be to add a daughterboard with an open-drain reset IC like the TLV840-Q1.

  • 0 in reply to Clemens Ladisch
    Intellectual 550 points

    1. can you explain why the point B might be high or low?

    2. Point B the pull low 1K is used for power on reset stage only. The point B is used as input direction for SOC UART TX output. Is the idea ok?

    3. Yes, let OE is controlled by RESET and high impedance. Got the point thanks.

  • 0 in reply to Alpha Ting
    Guru 317280 points

    A2 is pulled high, B2 is pulled low. It is random which one wins.

  • 0 in reply to Clemens Ladisch
    Intellectual 550 points

    How about the question (2)---Point B the pull low 1K.  It will force the Point B output driver always low at DC stage. When The point B is used as input direction for SOC gpio output. its level will follow the SOC gpio level. The ideal is right?

  • 0 in reply to Alpha Ting
    TI__Genius 9590 points

    Hi Alpha,

    If you add 1k ohm PD on A2, the A2 voltage depends on the SoC GPIO level.

    But A2 still could be low since the integrated PU inside SoC and that 1k ohm PD will form a voltage divider.

    When the A2 is driven from B2 side, then A2 voltage should be  1.8V*1k/(4k+1k)

  • 0 in reply to Alpha Ting
    Guru 317280 points

    It is possible that B2 reads high and then A2 tries to output high. The pull-down will work reliably only if OE is pulled low during power up.

    In any case, 1 kΩ is too strong; the RXD signal will no longer work.

    The only mechanism that works is one that pulls down during power up, but is inactive afterwards. This is why I recomend the TLV840-Q1.