SN74HCS594: SN74HCS594PWR_Input Clock SRCLK and RCLK

Tool/software:

Hello,

For Shift register part SN74HCS594PWR, there are two input clock pins which are Shift register clock(SRCLK) and Output register clock(RCLK). There is a serial Input "SER" pin.

1. While the external source is providing the serial data to SN74HCS594PWR, the serial data shall be in synchronous with "SRCLK" signal or "RCLK" signal?

2. The SN74HCS594PWR shall latch input serial data with SRCLK or RCLK?

3.What is the maximum input clock frequency range for SRCLK and RCLK?

4. There are two frequency ranges provided in datasheet, Clock frequency(fclock) in Table 6.6 and Max switching frequency(fmax) in table 6.7. what parameter should be considered for SRCLK and RCLK clock range?

5.There are no timing waveforms provided in datasheet to understand, what all signals are required while serial data is written into SN74HCS594PWR? Please provide any timing waveforms if available.