SN74AVC4T774: cascade SN74AVC4T774 for SPI application

Hector Chen

Intellectual 370 points

Part Number: SN74AVC4T774

Tool/software:

Hi Sir,

SPI clock rate around 5MHz

Do you recommend SN74AVC4T774 for the SPI application below?

What should we pay attention to in the application? for example, load capacitance

Do you have any requirements on the input signal of the level shifter? for example, rise time, fall time, etc.

Thanks

Hector

3 months ago

0 Joshua Salinas 3 months ago

TI__Genius 13620 points

Hello Hector,

Yes, I would recommend the AVC4T774 for SPI applications. Since it is SPI, I would pay attention to the distance between the master and slave since this will increase your propagation delay. 5MHz is typical for SPI but if you happen to have a long trace/cable length, you may experience missing bits.

For input requirements, I would follow the recommended conditions found in the datasheet.

Regards,

Josh

0 Hector Chen 3 months ago in reply to Joshua Salinas

Intellectual 370 points

Hi Josh,

Do you have examples showing missing bits when using long trace/cable length?

We will use a 130mm coaxial cable to connect main board and sensor board.

Thanks.

Hector

0 Joshua Salinas 3 months ago in reply to Hector Chen

TI__Genius 13620 points

Hello Hector,

This reference design (TIDUED8) notes talks somewhat about the effects of prop delay on SPI clock and how LVDS could be used to resolve it. However, this mainly applies to cable lengths >1m.

I don't see an issue with using a 130mm coaxial cable to connect main and sensor board.

Regards,

Josh

0 Hector Chen 3 months ago in reply to Joshua Salinas

Intellectual 370 points

Hi Josh,

Update the topology and list the number of slaves connected to the bus.

Do you have any concerns?

Thanks

Hector

0 Joshua Salinas 3 months ago in reply to Hector Chen

TI__Genius 13620 points

Hello Hector,

I don't see any issues with the updated topology. Thanks.

Regards,

Josh

Logic

Logic forum

SN74AVC4T774: cascade SN74AVC4T774 for SPI application