Tool/software:
Hi Support
There is a clock source (1.8V level, 100MHz from ASTMHTE-18-100.000MHz-AR-E-T), how to design with LSF level shift to get a 1.2V level 100MHz clock and fed into the target system? From the datasheet, I am confused about the application note like Figure 9-5 in datasheet (https://www.ti.com/product/LSF0101) for pull-up requirement. Or do you have any other suggestion?
This device works better with a voltage difference of at least 0.8 V. You can simply connect the Vref_B biasing circuit to a higher voltage; the pull-up voltage at the output can be different. For translating to a lower voltage, the pull-up resistor value does not really matter. (If you really have no voltage other than 1.8 V, then you must generate rising output edges with the pull-up resistor, and then you have to size it correctly, which is hard to do if you do not know the capacitance of your board, or if the signal source has a limited drive strength.)
It might be a better idea to a fast buffer with overvoltage-tolerant input like the SN74AUC1G125.