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Original question:

SN74LVC1G08: Output Logic Startup State

SN74LVC1G08: How to Ensure Logic High Glitch Free Power Up

Gregory Dieffenderfer
Prodigy 10 points
Part Number: SN74LVC1G08

Tool/software:

Hi,

I need to confirm if my implementation is guaranteed to avoid glitching at power up. I need the output to follow VCC (+5V). The ramp rate of VCC is about .5V/ms. I have both inputs tied to VCC via 4.99K resistors. From lab measurements, it looks like the output turns on around .5V and follows VCC, but I need to make sure this is the typical behavior and not luck of the draw. 

This strategy for glitch-free power up is suggested in one of the replies from this post:  SN74LVC2T45 power-up unintended driven output Can it be employed for this device as well?

Thanks.

  • +1
    TI__Genius 12981 points

    Hi Gregory,

    Our defined operation starts at 1.5 V as per the DS.

    That being said yes your pull-ups would force the output logic HIGH as soon as the VCC passes a threshold (which might vary from lot to lot) to turn on the transistors internal to the part. We do not specify what that threshold may be as you have found on these devices it is around 0.5V. This is the behavior I would expect of these devices, and I would not describe it as luck that it is behaving like this.

    To clarify you are experiencing expected behavior although the exact value the output turns on at may not be consistent as it is outside of our spec range for these devices.

    Regards,

    Owen

  • 0 in reply to Owen Westfall
    Prodigy 10 points

    Owen, 

    Thank you for the reply. My concern would be if the device could drive the output low due to undefined behavior before VCC reaches 1.5V. From your description of the part operation, the outputs are high-impedance until VCC reaches some threshold, then the output should drive high due to the pull-ups to VCC on the inputs. This is acceptable for our application. Thanks!