CD74HC4094: Using CD74HC4094 and CD74HC688 at 3.3 V for Pattern Detection and Timed Output Disable

Hi Nikki,

Thank you for the clarification regarding the OE behavior and capacitive load limitations.

In our design, an 8-bit serial code and clock from the controller are loaded into the CD74AC164BQAR shift register. The parallel outputs are compared against a fixed reference using an identity comparator CD74HC688PWR. When a match occurs, the comparator output goes low (active-low), which is inverted to generate an active-high decoded signal. This signal is required to remain stable for approximately 10–30 ms; therefore, an RC delay is used. After the delay, the signal drives a MOSFET that pulls the CLR pin low to reset the shift register.

Based on this operation, will this approach work as intended? We have attached the schematic for your reference.

Regards,

Sanfiya Banu M H.

DESIGN.pdf

Hi Nikki,

Thank you for the detailed review and the recommendation. I appreciate you pointing out the transition-time limitation of the 74AUP1G32GS and the clarification regarding Nexperia’s “Schmitt-trigger action” versus a true Schmitt-trigger input.

Based on your feedback, I have replaced the 74AUP1G32GS OR gate with SN74HCS4075QPWRQ1. This device provides true Schmitt-trigger inputs and is better suited to handle the slow input transition times present in our design, while also improving noise immunity and robustness. Please let me know if you see any concerns with this substitution.

I would also like to clarify one point regarding the operation of the CD74AC164BQAR shift register and its interaction with the comparator. If the shift register is not explicitly cleared before the first clock pulse, the first serial bit (LSB) will be shifted into QA, while the remaining outputs (QB through QH) will retain their previous or power-up default states. Since the comparator evaluates all eight outputs on every clock cycle, there is a concern that intermediate or partial data patterns during the shifting process could be incorrectly interpreted as a valid match.

Our requirement is that the comparator should assert a valid output only after all eight bits have been fully shifted in, i.e., after the eighth clock pulse, and only if the complete 8-bit pattern matches the reference. Could you please advise whether it is necessary to explicitly clear the shift register prior to loading the serial data, or whether the current configuration is sufficient? Additionally, what would be the recommended approach to prevent false matches during the intermediate clock cycles.

Regards,

Sanfiya Banu M H.

Hi Nikki,

Thank you for your suggestions and for pointing out the input requirements of the SN74HCS4075. We will ensure that any unused inputs are properly terminated to ground.

If we use the CD74AC164BQAR, What will be the default state of all the output pins from Qa to Qh after power up?  is there a functionally similar shift register that provides three-state (Hi-Z) outputs .

We initially considered the SN74AC595 because its storage register cleanly separates the shift operation from the output update, which effectively prevents false matches during intermediate clock cycles. However, due to GPIO limitations on our controller, we are unable to provide an additional dedicated RCLK (latch) signal. For this reason, we moved away from SN74AC595.Tying SRCLK and RCLK together on the SN74AC595 does not appear to be a recommended or robust approach. Could you please confirm whether this configuration is supported? If not, is there an alternative approach—such as using the same clock with a defined delay, edge-based gating, or minimal external logic—that would allow both SRCLK and RCLK to be derived from a single clock source while still ensuring correct and deterministic operation?

As an alternative, we selected the CD74HC4094, since its output strobe (STR) can be held enabled by default, allowing data to be shifted without requiring an extra latch control signal. While this simplifies the interface, the challenge we now face is that there is no straightforward way to asynchronously clear or force the outputs to a known inactive state after approximately 30 ms, which is required by our system behavior.

Any guidance on the most robust solution—either with the currently selected device or an alternative recommendation—would be greatly appreciated.

Thank you for your support.

Best regards,
Sanfiya Banu M H.

Hi Sanfiya,

Today is an American holiday, so I will get back to you tomorrow. Thank you for your patience!

Regards,

Nikki

Hi Sanfiya,

I would like to recommend TPLD2001 again. I think TPLD could incorporate this entire circuit into one device, and it is highly customizable. If you like, I can help you create this design for TPLD.

Tying SRCLK and RCLK together is no problem for any of the 595 devices. This is a common design. In this scenario, the output will always be one step behind the input. 

An alternative shift register is SN74HCS595. This is very similar to SN74AC595, but it has Schmitt-trigger inputs. This allows a slow rising edge on the input, so you can add an RC delay between SRCLK and RCLK. Take a look at  SN74HCS594: Hold time requirement of RCLK w.r.t. nSRCLR . In this thread, they are discussing nSRCLR and RCLK, but the same kind of thing can be applied to SRCLK and RCLK. That said, there is no problem with simply tying SRCLK and RCLK together.

You have enough GPIOs to use the OE pin, correct? Otherwise using this device doesn't make sense for your application.

Regards,

Nikki

Hi Nikki,

Thank you for the detailed suggestions and for recommending the TPLD2001. I appreciate the flexibility it offers, and it is something we can certainly evaluate in a future revision.

For the current design, I wanted to clarify the approach we are planning to proceed with. At this stage, we are planning to use the CD74AC164BQAR as the shift register along with the CD74HC688PWR comparator.

In our implementation, the same clock signal is applied to the clock input of the shift register and to the enable pin of the comparator. With this arrangement, the intent is that the comparator only performs decoding when the clock is low, i.e., during the period when no transitions are occurring in the shift register outputs. This avoids any false or intermediate comparisons while data is being shifted. Once all the required bits are correctly shifted in and the desired condition is met, the shift register is cleared after a delay of approximately 30 ms.

Please note that, due to GPIO limitations on our controller, we do not have a dedicated GPIO available to control the enable or output control of the shift register. As a result, the shift register remains enabled at all times in this design.

I have attached the schematic for your reference. Kindly review it and let me know if you see any concerns or recommendations with this approach.

Thanks again for your support and insights.

Regards,
Sanfiyadesign (1).pdf

Hi Nikki,

Thank you for the review and for the helpful suggestions.

Noted regarding the thermal pad of U69. We will review the layout and connect it appropriately if required.

Also, thank you for pointing out the requirement to terminate unused inputs of the SN74HCS4075QPWRQ1. We will ensure that all unused inputs are tied to ground as recommended.

For this OR gate, we are using a 3.3 V input level where the input pins are driven by an RC delay network (20 ms, based on the 63% time constant). While reviewing the datasheet, we noticed that the exact VIH level is not explicitly specified for 3.3 V operation. Additionally, the Schmitt trigger thresholds (VT+ and VT−) are not directly listed for 3.3 V, and the VT+ range given for nearby supply levels appears quite wide (1.7 V to 3.15 V).

Could you kindly advise what voltage VIH should be considered when designing the RC delay circuit ? It would be helpful if you could also verify whether the RC delay implementation in the previously shared schematic is appropriate for this device.

Thanks again for your guidance and support.

Regards,
Sanfiya Banu M H.