SN74LV125A - ICC Question

I wouldn't expect Icc to change (as far as device quiescent current). There might be some change in Iin through the input, which if 5V and Vcc=3.3V, would flow back through the ESD diodes. The datasheet doesn't provide an I/O schematic, so I'm not sure if the input to Vcc current path exists in these parts.

I_CC is the quiescent current of the device and per the data sheet is independent of (not affected by) the voltage on the Inputs whether higher or lower than V_CC (as long as you stay within abs max ratings.)

I_I is the current into/out of an input and per the data sheet is independent of V_CC as long as you stay within abs max ratings. The input-to-V_CC current path speculated above does not exist as long as you stay within absolute maximum ratings. This is what allows this device to be used for level translation.

You are verifying that there are no protection diodes between input and Vcc pins. Correct? Thus the input transistor stages are designed to have breakdown voltages greater than the max ratings. Fine.

But at a physics level, Iin coming in/out of the chip has to flow through either the Vcc of Gnd pins of the device. (Where else would it come from?) When the input is low, Iin is drawn from the Vcc pin through the internals and out the input pin. Same thing with a high input and the Gnd pin.

Please read the "Understanding Advanced Bus-Interface Products" Design Guide, as shown beginning on page 4, no current flows from VCC when IN is at a steady state: http://www.ti.com/lit/an/scaa029/scaa029.pdf .   

-Leonard

Analog Applications - ACAT Dallas

Leonard,

Well then, you have some conflicting documentation now, don't you?

Looking at the datasheet for the part in question, SN74LV125A, it says that Vin can go to 5.5V regardless of Vcc. Yet the document you referenced, in Figure 3 shows an ESD protection diode for LV families (and states "NON-5-V-TOLERANT" in big capital letters!) So.... which is it?

Assuming for a minute that the 'LV125A device has an input stage more like the 5-V-tolerant LVC/LVT/ALVC  structure shown in Figure 3, then the input ties to a set of complementary CMOS transistors. So exactly where does the gate leakage current flow to from if not from Vcc or Ground?

When Vin is Low, there is gate leakage current from Vcc through the PMOS gate out the Vin pin. When Vin is high, there is gate leakage current through the gate of the NMOS transistor into Vss.

It's physics. Just because it's negligible compared to the Icc quiescent current doesn't mean it doesn't exist.

TI defines  The range of input voltage levels over which the logic element is specified to operate. (VI min) and (VI max) values are used as test conditions for the II, ICC, Ci, and Cio test. 

Looking at the datasheet Ii is specd to Vi max. So the input up to 5.5V does not effect Ii. This is tested.      

   This part also has Ioff feature which allows inputs or outputs to be powered when Vcc is 0V. See attached.  So on this test we sweep the input from 0V to (Vi max) to show no leakage occurs when Vcc is 0V. Icc test only tests up to Vcc but this Ioff leakege covers it the rest of the way up to (Vin max).

LV devices do not have a clamp diodes to Vcc wich allows the input voltage to go above Vcc without leakage. 

Yes the appnote is incorrect. There are several very old appnotes out there that need to be cleaned up. I beleive the LVxx family was actually changed at some point.

And you are correct there will be some leakage to Vcc and gnd but it will be within spec.

I realize that this discussion devolved into something more than the original question asked, but when presented with a 17-year-old document as backup to a statement, and that document said actually the opposite of the argument being made.... well, I just don't have the willpower to not respond. :-)

I understand Brian, and I would do likewise!  Thanks for the feedback, much appreciated, very much a good reminder that we do indeed have some documentation to revise. 

-Leonard

Hello all,

The thread got derailed a bit from the original question which Rustin had posted on the forum for me.  I am most interested in the effects of ICC over the range of VIN for SN74LV125A.  It is only specified at VIN = VCC (5.5V in the datasheet) and VIN = 0V.  In my application, VCC is 3.3V and VIN is 5V.  Please verify ICC will not exceed +/- 20uA per channel at VCC = 3.3V and VIN = 5V. 

I wanted to verify this information because I am also using SN74LV125AT in a 3.3V to 5V level-shifting application.  The datasheet for SN74LV125AT has an additional line item for delta ICC which shows an ICC variation due to changes in VIN (e.g. a change of up to 1.5mA in ICC with VCC at 5.5V and VIN at 3.4V).  I want to verify whether this same phenomenon must be specified in the SN74LV125A.

Thanks,
Bryan

here is a general comment but I dont have exact data.

Icc is specd at the rails. 0V and Vcc. Icc will be lowest here.  Delta Icc is moved away from the rails to show what Icc values you would have if you had a TTL input. It will be much higher. The closer you get to the switching threshold the more Icc you will see.

The LV125AT has TTL level threshold and is allowed a 3.4V input.  The LV125A has CMOS inputs which put the threshold at Vcc/2.  Vih will be Vcc*.7 whic is 3.85V at 5.5V Vcc.  So a 3.4V input is not allowed..

The lv125A will have higher Icc (delta  Icc) as you get closer to the threshold but it is not specd.

So, in my application for the LV125A where VCC = 3.3V and VIN = 5V, I should see ICC values within the +/- 20uA per channel that is specified in the datasheet since VIN at 5V is nowhere near the switching threshold with VCC = 3.3V...correct?

correct

If the Vin is from Vcc to the Vi max it will be within the Icc spec.