SN74LV8154 clock and timing questions

Dear Community,

concerning the SN74LV8154 counter device, listed below a few questions:

Question 1: max. clock frequency

Datasheet states:
f = 25 MHz (as min. value ... there is no max. value given)

TI-website states:
max. 70 MHz at max. supply voltage

--> which value is correct ?

Question 2: RCKL to Y timing

Datasheet states:
max. 27 ns @ 5 VDC (which would mean 2x27 ns = 18.5 MHz)

Assumption: if a clock of 70 MHz would be correct, the
internal counting could have a max. speed of 70 MHz, just
the readout of the finally reached value at the end of the counting process
has to be slower, with a max. speed of 18.5 MHz

--> is this assumption correct ?

Question 3: pulse duration tw for CCKA(CLKA), CCKB(CLKB), RCLK

Datasheet states:
min. 10 ns for each state, high or low

--> this means a max. frequency of 2x10 ns = 50 MHz as clock speed can be used ?

Question 4: RCLK readout behaviour

Timing diagram in datasheet shows:
The reached counting value will be put to the output when RCLK goes from low to high.
As long as RCLK remains high, no further value update will reach the output ?

The RCLK needs another high-low-high transition to fetch the next achieved counting
value to the output ?

Thank you very much in advance.

Rgds. Peter