high-impedance state for SN74CB3T3245

Hidetoshi Matsunami

Expert 2750 points

Other Parts Discussed in Thread: SN74CB3T3245

Hello Team,

I'd like to ask you about SN74CB3T3245.

I understood that a high-impedance state exists between the A and B ports when /OE is High and Vcc=0V.

Is my understanding correct?

Also does a high-impedance state exist between the A and B ports when /OE is Low and Vcc=0 to 3.3V?

How many supply voltages is High-Z state of A and B ports canceled when /OE is Low and Vcc=0 to 3.3V if so?

Best Regards,

Hidetoshi Matsunami

0 C. Ryan Land over 9 years ago

Hi Matsunami-san, the "IOFF" feature protects against current flow when VCC = 0 and provides isolation between the inputs and outputs.

See the following application note for more information on IOFF: http://www.ti.com/lit/pdf/szza033

0 Hidetoshi Matsunami over 9 years ago in reply to C. Ryan Land

Expert 2750 points

Hello Ryan,

Thank you for your reply.

I'd like to ask you an additional question.

During Vcc is ramping from 0V to 3.3V, what voltage are I/O ports of SN74CB3T3245 High-impedance state until?

I think VCC threshold levels are not specified in data sheets for CB3T Family.

Best Regards,

Hidetoshi Matsunami

0 Hidetoshi Matsunami over 9 years ago in reply to Hidetoshi Matsunami

Expert 2750 points

I edited my additional question.
I'm looking forward to hearing from you.
Best Regards,
Hidetoshi Matsunami

0 C. Ryan Land over 9 years ago in reply to Hidetoshi Matsunami

Hi Matsunami-san, we do not have that specific voltage but it is usually around 1.5 V. The customer will need to run tests to confirm.

0 Hidetoshi Matsunami over 9 years ago in reply to C. Ryan Land

Expert 2750 points

Hello Ryan,

Thank you for your support.

I understood it.

Best Regards,

Hidetoshi Matsunami

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