This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hello Team,
I'd like to ask you about SN74CB3T3245.
I understood that a high-impedance state exists between the A and B ports when /OE is High and Vcc=0V.
Is my understanding correct?
Also does a high-impedance state exist between the A and B ports when /OE is Low and Vcc=0 to 3.3V?
How many supply voltages is High-Z state of A and B ports canceled when /OE is Low and Vcc=0 to 3.3V if so?
Best Regards,
Hidetoshi Matsunami
Hi Matsunami-san, the "IOFF" feature protects against current flow when VCC = 0 and provides isolation between the inputs and outputs.
See the following application note for more information on IOFF: http://www.ti.com/lit/pdf/szza033
Hello Ryan,
Thank you for your reply.
I'd like to ask you an additional question.
During Vcc is ramping from 0V to 3.3V, what voltage are I/O ports of SN74CB3T3245 High-impedance state until?
I think VCC threshold levels are not specified in data sheets for CB3T Family.
Best Regards,
Hidetoshi Matsunami
Hello Ryan,
Thank you for your support.
I understood it.
Best Regards,
Hidetoshi Matsunami