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Schmitt-Trigger Input Levels on 74LVC123

Ulrich Schmidt49
Intellectual 340 points

Hi TI e2e,I need to determine the rise time for the Schmitt-Trigger Inputs (A_N/B) of the 74LVC123, however, there are no threshold levels in the datasheet.
My customer is diving the input via a R/C network, hence it would be good to know the min/max threshold levels.

Can we assume that the levels can be taken from a 74LVC14A?

Best regards,
Uli

  • 0
    TI__Guru 59880 points
    Hi Uli,

    I do not have the numbers with me . This is indeed strange that other multi vibrators don't have them rated either .
    You can take the threshold information from the snLVC1G14 as the reference.
  • 0 in reply to ShreyasRao
    Intellectual 340 points
    Hi Shreyas,
    some follow up question I hope you can help me with:
    In our circuit A_N and B can be seen as static. Approx 500ms after Battery Power is applied, a rising CLR_N (stay high) shall generate a dedicated output pulse. SN74LVC1G123YZPR VCC is stable after BAT_PWR (VCC derived from BAT_PWR).
    With a CLR_N rise time of ~30µs the output pulse won’t be generated with >0.63% failure rate. Retesting these failed devices with 30ns rise time, they pass.

    From several sources I got the information, the recommended transition time for LVC logic is 10…20ns/V at 1.8V (relevant for CLR_N, not for Schmitt input). So far we would need to meet 20…40ns rise time on CLR_N. Here I’m not sure if it’s a recommended value or a real limit, SN74LVC1G123YZPR data sheet doesn’t explicitly describe it.

    According CMOS principles, I would expect, when violating these limits e.g. with 30µs, the current consumption in CLR_N input buffer will rise up to mA range during transition, nevertheless the rising CLR_N input should trigger the output pulse.

    Have some more detailed questions:
    - What is the CLR_N transition time, recommend and max rating ?
    - What is the expected SN74LVC1G123YZPR behavior when violating the transition time regarding
    a) output pulse
    b) current consumption
    c) life time
    d) other topics
    - Is the device behavior correct, means not generating the output when violating the rise time ?
    - Is our use case valid ?
    It’s not specified in the data sheet: on SN74LVC1G123YZPR start up, CLR_N is low while B changes to high, VCC is stable after B change, 500ms later CLR_N rises and shall trigger the output.
    - does a slow rising VCC (<10ms) may cause any/similar issues ?
    - does the state B=0.5…4.5V while VCC=0V cause an issue ?
    - does the state B=0.5…4.5V while VCC=0…1.8V cause an issue ?
    - does the state B=0.5…4.5V while slow rising VCC 0…1.8V cause an issue ?

    Best regards,
    Uli