SN74LV164A output delay

Hi David!

Have a look at chapter 6.9 and following in the datasheet - they list the switching characteristics for different voltages. But you cannot look for A -> Q because the input requires CLK, so look for CLK -> Q. A can vary from high to low without changing Q as long as CLK does not change from low -> high.

Dennis

Dennis,

Thanks for you reply.
You mean when A is high, If CLK->rising edge then Q->high.
Is it correct? Then delay time is xx ns.

Thanks.

David Park said:

You mean when A is high, If CLK->rising edge then Q->high

Yes, exactly. A and B can change their levels, but you will not see this at Q. Only with a rising edge of CLK, Q will become high when A and B are high or low when A or B or both are low. Of course we are only talking about Qa, the others will be whatever their preceding Qx was. And CLR has to be high, of course.

Dennis