Hello There,
I would like to confirm whether my understanding from below truth table of R-S latch is correct.
Thanks.
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Hello There,
I would like to confirm whether my understanding from below truth table of R-S latch is correct.
Thanks.
Hi Ryan,
I assume you are ignoring the enable input (tied to VCC?), and I'm not sure why you repeat states here -- is this some representation of your system?
The one line that I would be concerned with is the S0 = 1, R0 = 1, Q0 = 1 line. If you were to drive both S and R high, the output will be 1, however, if you release both simultaneously, back to 0, the output will be 'unknown.' I would recommend avoiding that situation with any SR latch.