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Hi,
I use PC2 of CD74HCT4046 as the phase detector, PC2Out output drives a VCTCXO after RC filtering.
According to the datasheet, PC2out is an edge-triggered JK flip-flop output.
The positive and negative pulses are output when the Sigin and Compin edges are relatively advanced and delayed respectively, and the remaining states remain unchanged.
However, in the actual circuit test, the PC2Out pulse output is normal. In the high-impedance state, PC2Out should theoretically remain unchanged, but the actual result is that PC2out falls to 0 level in the high-impedance state, so that the accumulation of phase error cannot be formed. Finally, only a very small level is obtained after filtering, and the VCTCXO does not normally drive the frequency adjustment to form a phase lock on the GPS signal.
Blue is PCPout waveform and yellow is PC2out waveform
Hi Dylan,
Yellow is PC2Out, blue is PCPout, purple is Sigin, and light blue is ComPin
It can be seen that PC2out rises and maintains normally, but when PCPout is zero, PC2out quickly falls to 0 level.
In theory, the RC parameters should not change, the rise time and fall time should be the same, but the fall time in the above waveform is obviously faster than the rise time.
As a result, PC2out is reduced to 0 leve . l during each PPS period, and the error signal forms a periodic fluctuation and cannot be accumulated.
