• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 2 answers
  • Subscribers 18 subscribers
  • Views 958 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74LVC2G17: SN74LVC2G17

Siddharth Sangam
Intellectual 640 points
Part Number: SN74LVC2G17

I am calculating Power dissipation of SN74LVC2G17-Q1 , need to know about the device operating current.

Also do you have any app note to calculate power dissipation of digital IC please send it.

with regards,

Siddharth Sangam

  • 0
    TI__Guru* 96947 points
    Hello Siddharth and welcome to the forums!
    Details on calculating power consumption for your typical CMOS device operating with fast edges and consistent frequencies can be found here: www.ti.com/.../scaa035b.pdf

    That doesn't include information about what happens when you have slow edges or input signals that stay near the thresholds -- which is a common way to operate Schmitt-trigger buffers. If you can give me some details about your application, i can try to help with an estimation of power consumption for you.
  • 0 in reply to Emrys Maier
    Intellectual 640 points

    Hi,

    Thanks for your reply for providing app-note.

    (Power dissipation using app-note formula is coming in micro-watts - need to confirm)

    So, I also need device operating current for analysis.

    Please provide it.

    regards,

    Siddharth Sangam

  • 0 in reply to Siddharth Sangam
    TI__Guru* 96947 points
    Hello Siddharth,
    What do you mean? All required values are given in the datasheet. Are you having trouble finding a particular value?

    You haven't provided me any values or equations, so there's no way I can help....
  • 0 in reply to Emrys Maier
    Intellectual 640 points

    These above values are given in datasheet.

    I am designing circuit for 100uA output current.

    I need to calculate the power dissipiation for it if signal frequency is 50KHz 

    Design consideration using app-note

    Vcc =5V  Icc = 10uA as per app-note quesient current must be consider.

    C.PD = 21pF as per datasheet

    C.L = 50pF

    Input frequency Fi = 50KHz

    Output Frequency = 50KHz

    So,by above calculation I am getting 0.05mW power dissipitation.

    This is the value coming after calculation using app-note.

    Can you check this whether it is right or suggest how to calculate power dissipiation when using 2 channel and when using only single channel.

    Siddharth Sangam

  • 0 in reply to Siddharth Sangam
    TI__Guru* 96947 points

    Hey Siddharth,

    Thanks for the details - now I can help.

    The equations you have are missing a couple of things. Everything required is in the application report I linked and the datasheet, plus the values you gave me.

    The static power at 5V is given by equation 3:  

    P_S = V_CC * I_CC = 5 * 10 uA (max) = 50 uW (max)

    The dynamic power at V_CC =5V  , C_L = 50pF, N = 2 (# of channels switching), F = 50 kHz

    Transient power consumption is given by equation 4:

    P_T = C_pd * V_CC^2 * F * N = 52.5 uW

    Capacitive load power consumption is given by equation 5:

    P_L = C_L * V_CC^2 * F * N = 125 uW

    Total dynamic power is given by equation 7:

    P_D = P_T + P_L = 52.5 uW + 125 uW = 177.5 uW

    Total power consumed is given by equation 10:

    P_tot = P_static + P_dynamic = 50 uW + 177.5 uW = 227.5 uW

     


    If you'd like to go one step farther, we can calculate the expected temperature rise of the device at this power rating.

    The change in temperature is determined by R_θJA and the power being consumed by the device. I will use the worst case R_θJA, which is 300C/W using the DSF package.

    delta_T = R_θJA * P_tot = 300C/W * 0.0002275 W = 0.06825 C

    So, if you were operating the device at 40C, you can expect that the junction temperature will be 40.06825 C, approximately.  This isn't exactly surprising, since passing a signal through a single CMOS logic gate costs very little power.

  • 0 in reply to Emrys Maier
    Intellectual 640 points
    Thanks for the reply.

    My point for this is if we are using Dc signal ( zero frequency ) .
    Then dyanamic power dissipitation will be zero.
    Only static power dissipitation will be there.

    But static power is also in micro watt.

    Need to understand the exact calculation considering output current I.o = 4mA .what will be the power dissipation.

    As by above formula there is no consideration of output current.
  • 0 in reply to Siddharth Sangam
    TI__Guru* 96947 points

    Hi Siddharth,

    I see. You aren't using the device to drive a signal into a CMOS input, but are using it to provide a DC current, probably to an LED?

    A DC output current of IO = 4mA will increase the supply current by 4mA, however the power consumption will not be increased by VCC * IO.

    The correct power calculation would be:

    Pdiss = ICC * VCC + (VCC - VOH)*IO

    Note that VOH is dependent on the output current. It's probably easier to just use an approximation of the on-state resistance of the p-FET on the output, so instead of having PDC = V*I, you get PDC = I2 R

    rON for the LVC family can be estimated as 15 ohms (typical), so the easier equation is:

    Pdiss = ICC * VCC + I2 * 15