Other Parts Discussed in Thread: SN74AUCH16244, SN74AUCH244
I am using the SN74AVCH20T245 in the following configuration:
- Data from B --> A
- VCCB = 2.5 V, VCCA = 1.8 V
- 0.1uF, 0402, decoupling cap on each of the 4 power pins, on the backside of the PCB underneath the BGA footprint
- 16 bits = single data rate data clocked at 156.25 MHz
- 4 bits = 2 complimentary clock signals at 156.25 MHz
The clocks are always toggling.
In a particular test pattern case, the data bits are static for many clock cycles, then toggle for a few clock cycles. Think of it like a data packet with a static payload, but a changing header with each packet.
During the static data portion of the packet, the clock signals look normal. However, when all 16 bits of the data begin to toggle, the P-side clock signals (only, not the N-side) show dramatic amplitude droop for ~3 clock cycles. So much of a droop that the receiving FPGA (connected to the HA01P/N signals in the above picture) do not register a clock transition.
I have read app note szza029b that describes the simultaneous switched output & crosstalk behavior of the VFBGA package and it looks reasonably good.
Any tips on where to look for the root cause of this issue? Thanks!
