Hi Sirs,
Sorry to bother you.
We have use two TI logic as below, the main application is the frequency division ( ÷ 2).
Could you help review schematic and check is this schematic will suitable for our application?
Thanks!!
Schematic:
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Hi Sirs,
Sorry to bother you.
We have use two TI logic as below, the main application is the frequency division ( ÷ 2).
Could you help review schematic and check is this schematic will suitable for our application?
Thanks!!
Schematic:
Hello,
It looks like this will work fine, however since the preset and clear pins on the flip flop are not necessary here, you might consider the SN74AUP1G80 which only needs 5 pins and would save a little space. Also since you are not using the voltage level translation functionality of the buffer, another good option is the SN74AHC1G125.
regards,
Gabriel
Hi Sirs,
Thank you quick feedback.
Could you help check again that Picture 2 or Picture 1 , which one is correct ?
One more question , as I know that divide-by-2 Counter
It can be seen from the frequency waveforms above , that by “feedback” the output from Q to the input terminal D, the output pulses at Q have a frequency that are exactly one half ( ƒ/2 ) that of the input clock frequency.
So , Modify the schematic as below Picture 2 .
Picture 2 : Modify.
Picture 1 : Before.
It does not matter whether you are using Q or Q for the output. They are the inverse of each other, and since you are not using PRE or CLR, your circuit does not care about the phase.
(The '80 would have only Q.)