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Original question:
The previous answer makes sense, but doesn't seem to quite cover all situations. Assume the following scenario with VCCA=1.8V and VCCB=3.3V, so Tdis(a)max = 40ns, Tdis(b)max =60ns, Ten(a) = 19ns and Ten(b) = 10ns
Case 1 - direction changed before outputs are disabled. Concern is both sides are enabled simultaneously.
1) DIR=H and OE=L to drive A to B
2) OE then set to '1' and output B starts to disable (take up to 60ns)
3) 20nsec after OE=H, DIR=L (B to A now). At this point I assume that both A and B could be enabled for up to 39.5ns (Tdis(b) - 20nsec arbitrarily chosen - Ten(a)min) (probably not that long since it is unlikely that Tdis(b) would hit max and Ten(a) would achieve minimum values). If this is correct then it is probably true that DIR should not change prior to Tdis(x) after OE or else both sides could be enabled simultaneously (which may not be a problem if everything else is off at the same time, but at this point no one is particularly controlling what the state of the IO should be and it is possible, maybe not probable, that strange things could occur).
Case 2 - direction is changed while device is disabled, but then enabled quickly after direction is changed. Concern is it may be unknown if the direction changed before outputs are enabled.
1) DIR=H (A to B) and OE=H (disabled). It has been in this state long enough to know that the Tdis(x) timing has been satisfied.
2) DIR now set to L (B to A). Since everything is already disabled from the previous step, I would assume that Tdis(x) no longer applies again. But I also assume there is a little time required for the logic in the top block to switch and that is not detailed out..
3) OE is now set to L 5 nsec later. At this point then it takes Ten(a)=19nsec to actively be driving the output (assuming there is no real delay required to be satisfied by the previous step that is longer than 5 nsec that was arbitrarily chosen for this example delay)
In case 2, without any information from the datasheet regarding the direction logic delay, it is impossible to know when OE can be set L after changing the direction without risking the wrong side being enabled. It may be safe to assume that the delay in the control logic is the same for both inputs, in which case there shouldn't be any issue. And even if there is some small difference in the delay it is very short. However when looking at section 6.6 (VCCA=0.7, VCCB=0.7V) things take a LONG time to happen (up to 170 nsec). I am assuming most of that time is required for the buffers to drive the lines and not the logic internal to the device, but that is not defined.
