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SN74LVCH16T245-EP: Output state During Power Up

Aidin Haddadi
Expert 1085 points
Part Number: SN74LVCH16T245-EP

Hi 

I am using some SN74LVCH16T245-EP for level translating from 3.3V (port A) to 5V (Port B). It is indicated in the datasheet that the control signals (#OEn and DIRn) are related to VCCA which is 3.3V in my case. There is also indicated that "To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor." This situation is observed in the PCB. 

In the voltage sequence, first we connect 5V (VCCB) and then 3.3V (VCCA). During the power up, all the input ports (to the IC) are zeroed and the #OE1 and #OE2 are tied to VCCB and we saw all the outputs going HIGH!

We expect the outputs be in high impedance, but all of them are going high.

We put 10K Ohms pull down resistor on the output pins, but the signal goes high again. I changed the pull down resistor to 1K Ohms, and we just saw a narrow glitch (and this is expected because it takes  a time for the VCCA be active and the control circuitry could detect that its outputs are disabled.)

The main problem is: Why outputs are all in HIGH state when #OEn are tied high and why we need lower resistor to pull it down?

  • 0
    TI__Mastermind 44170 points

    Hey Aidin,

    As you said it takes time for the control circuitry to get enough headroom to disable the outputs. The stronger pull-downs will help reduce glitches for two reasons: the amplitude won't be as high (you essentially will have a voltage divider at the output with the Rdson of the PFET) and the speed at which it will drive the line low once the outputs are disabled will be faster since you will have a smaller RC. Both of these would factor into to smaller glitches.

    I will also note, it is not recommended for this device to have pull-ups or pull-downs on the I/Os since they have bus hold.

  • 0 in reply to Dylan Hubbard
    Expert 1085 points

    Hi Dylan

    The best solution is we do not connect VCCB before VCCA and OE#, but I can not change the PCB at this time. I have tried to add some pull down on the output (I do not need bus-hold), there is a glitch with 400us width in my setup on the output. It seems the high-z state is not followed in this device!

  • 0 in reply to Aidin Haddadi
    TI__Mastermind 44170 points

    Hi Aidin,

    It's likely the bus-hold circuit exacerbates the issue since its function is to hold a logic state. However, there is no way to guarantee the outputs won't glitch during power-up. The best thing to do is to limit the amplitude of the glitch as much as possible prior to the output enable circuitry disabling the outputs.