SN74AUC1G79: OUT high ISSUE when D is low

James Zhan

Other Parts Discussed in Thread: SN74AUC1G79, SN74AUC1G74

rt Number: SN74AUC1G79

Hi team,

My customer is using SN74AUC1G79 in their design and the schematic as below.

They found that when the D and CLK are low, and power up the VCC, the Q will be high at the same time as below waveform.

Could you please help to check any thing goes wrong?

Thanks.

0 Clemens Ladisch over 4 years ago

Guru 267140 points

To be able to initialize the flip-flop without a clock pulse, use a device with asynchronouse clear/preset inputs, such as the SN74AUC1G74.

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