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SN74LV8154: Maximum frequency for SN74LV8154 configured as a 32 bit counter?

Roger314159
Prodigy 20 points
Part Number: SN74LV8154

The SN74LV8154 may be configured as a 32 bit counter by connecting CLKBEN to RCOA allowing a ripple carry between the two 16 bit counters.  Since these are ripple counters and not synchronous counters, would it be a correct understanding that the maximum clock frequency in the 32 bit configuration would be half that in the 16 bit configuration? For example, the part is rated at minimum 25Mhz at 3.3v and CL=50pf, so in 32 bit configuration could only 12.5MHz be achieved? This seems to make sense given a doubled propagation delay. This question is basically a reality check to make sure I'm not missing something fundamental. Thanks in advance for your help!

  • 0
    TI__Expert 6680 points

    Hi,

    No, this device will still support the rated clock speed (e.g. 25MHz @ 3.3V).

    Thanks!

    Chad Crosby

  • 0 in reply to Chad Crosby
    Prodigy 20 points

    Thanks Chad. But may I ask for clarification? Each of the two 16-bit counters has a propagation delay.  When cascading them together to form a 32-bit counter, since there is a ripple carry between the two banks of 16-bit counters, the total propagation delay must double.  The output of the first stage must settle before the second stage can process a possible carry and count with a second propagation delay.  This MUST increase the total system propagation delay by a factor of two, cutting the maximum frequency by half.  The question is then, whether the max frequency rating of the device is for each 16-bit counter when operated separately, or when the two are cascaded together.  If the former, that would be conventional.  If the latter, then that would be very unusual.  It would imply that if two cascaded counters could operate at max 25MHz as you imply at 3.3v and CL=50pf, then each one alone not cascaded could operate at 50MHz, which seems very unlikely.  So unless convinced otherwise, I think the device rating max frequency is for one of the 16-bit counters separately, not the two connected together, which implies a 12.5MHz max frequency when cascaded.  Can you please explain your reasoning as to why you think this is not the case?  Please tell me the error in my analysis.  Thank you.

  • 0 in reply to Roger314159
    TI__Expert 6680 points

    Hi,

    So the way that the 32-bit counter functionality is enabled is the following: CCKA & CCKB are both tied to the same CLK input, and RCOA is tied to the CCKBEN pin. This means that once every 2^16 clock cycles, the RCOA pin will switch, enabling a count on counter B. This RCOA pin will only activate counter B for 1 clock (CLK) cycle, thus only allowing 1 count on counter B. If you refer to the timing diagram from the datasheet (section 6.9), you'll see that both counters are capable of handling the same input clock. Also note that the current count of the counters is only available after RCLK has been pulsed.

    Thanks!

    Chad Crosby