2N7001T: 20MHz Clock Translator

Dear Ladisch,

Thank you for your reply.

Dear TI team,

I want you to answer my question.
Is it the same answer as Mr. Ladisch above?

Regards,

Y.Ottey

Dear Dylan,

Thank you for your reply.

I would like to ask adding question.

When converting from 1.8V to 3.3V at 20MHz, what is the difference between the rising rate (falling rate) ⊿V/⊿t of the input and output waveforms?

Regards,

Y.Ottey

Hey Ottey,

I'm a little unclear on your question. Are you asking about the recommended input transition rate spec?

Hey Dylan

Thank you for your reply.

My explanation was insufficient.
I would like to know how much difference between ⊿Vin/⊿tin and ⊿Vout/⊿tout comes out when converting the voltage level of 20MHz clock from 1.8V to 3.3V.
(Of course, the condition is that the recommended value of Input transition rise rate is max.100ns/V.)

I am glad if you can tell me because the reference value is okay.

Regards,

Y.Ottey

Dear Dylan

Thank you for your reply.

I have additional questions.

I was told the other day that it is possible to convert the voltage level of the 20MHz clock from 1.8V to 3.3V using the 2N7001T, but when I checked the data sheet, there was no specification for the frequency of operable signals.
Is there any reason to support the 20MHz clock?
(Or, if you can show the reason in the data sheet, please let me know.)

Our customers are considering the 2N7001T and I have been asked by them why the 2N7001T can support a 20MHz clock, so I would be happy to let you know.

Regards,

Y.Ottey

At these voltages, the maximum propagation delay (t_pd) is 14 ns. A 20 MHz clock has 25 ns between signal edges.

Dear Ladisch,

Thank you for your reply.

As shown in the figure below, when you input a 20MHz clock (25 ns between signal edges), the tpd of the device is max.14ns, so there is no delay of more than a half cycle of the clock. Is it all right to recognize that it corresponds to?

In other words, is it okay to recognize that a clock with a time between signal edges of 14ns or less (frequency 36MHz or more) is not supported?

Dear TI teams,

The reason why it supports the 20MHz clock is considered above, but is it correct?

Regards,

Y.Ottey

Correct.

But using t_pd to derive the maximum frequency results only in a theoretical minimum; the actual maximum frequency is likely to be higher than 36 MHz because the input can change even before the output has finished driving to the target voltage. But TI has not specified this.