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CD74HC4046A: Instability across whole band

Part Number: CD74HC4046A
Other Parts Discussed in Thread: CD4046B, SN74LV4046A

We need to use the CD74HC4046 in an already successful design of an instrument that uses an HCF4046, as the HCF4046 is now unobtanium.   The PLL is used with a TI CD40103BE to make a 100X frequency multiplier. 

VCC is 5V.

Pin 14 input is a 5V square wave (50% duty cycle) ranging from 128-2048 Hz..  Thus the PLL output on Pin 4 is 12,800-204,800 Hz. 

PROBLEM: No matter how we configure it, either the high or low end of the frequency range is unstable.  The output is stable enough for a frequency counter, but the instability is seen on the scope as a fast vibration, either shaking the waveform itself, or displaying a ghost wave out of phase with the bright waveform.  The instability occurs when the voltage at Pin 9 is below 0.9V or above 4.53 volts.  This is close to the limits noted in the spec sheet, that states that Pin 9 (VCOin) should be kept between 0.9 and 4.1 volts.   

QUESTION:  For this frequency range, what is needed to assure that Pin 9 is kept between 0.9 and 4.1 volts?

QUESTION: Spec sheets indicate this PLL is capable of 100,000:1  frequency range.  Our requirements are only 2048/128 a 16:1 frequency range.  How can  we fit that into 0.9-4.1 volts on Pin 9?

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I've tried various values, and the following two independent cases come closest to working.

C1: Case 1 = .06 uF,  Case 2= 220pF

R1: Case 1 =3.9K,  Case 2=200K

R2=NC (infinity)

R3:  Case 1 and Case 2 =100K (PIn 13 to Pin 9)

C2: Case 1 and Case 2 =22uF (loop filter capacitor)

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Thank you in advance for your help.

  • Hello Tom, and welcome to the forums!

    Are you trying to directly control the VCO with a voltage or are you using the device as a PLL?

    There are minor differences between '4046 devices - especially relating to the VCO section. What was stable on one may not be quite so on another.

    Since the HCF4046 is a 3 to 20V device, it's likely that the closest match you will find in our portfolio is the CD4046B.

    You could also try the much newer SN74LV4046A, which has better linearity than the older designs.

  • Thank you .  I didn't realize that the CD4046 was still active and that just may solve my problem.  

    To answer your question, the device is being used as a PLL in the normal configuration for integrating a divider chip.   With  5V VCC, It seems that the 74HC4046 is the only PLL I've seen that requires VCOin to be limited to 1-4 volts, which puts limits on the frequency bandwidth that I don't see in the literature on the CD4046 and others.  I've ordered CD4046 and we'll see it that works as well as the HCF4046.

    The graph below is from page 23 of scha-003b.  Note that the bandwidth in every case from from 1-4V at VCOin is such that the highest frequency is no more than 4X the lower frequency.  Is this range the most that this chip can do?  The reason I ask is that we need our highest frequency to be 16X the lowest.   We keep trying because we do achieve16X with the 74HC4046, just without stability.   Now I suspect this chip is not capable of satisfying our needs.  If 16X exceeds the TI designer's goals, I been beating a dead horse and might as well know that now.   I glean from your response that the 74HC4046 may not be suited for our needs.  Does the graph below unequivocally indicate that a 16:1 frequency ratio is not possible with the 74HC4046?

    As a test, I disconnected R2 that was connected from VCOin to GND.   I connected a variable voltage to  Pin 9 to run the VCO directly.  Indeed, the VCO output range was limited similar to range of the graph.   Does that test put the nail in the coffin that we'll never get 16:1 out of the 74HC4046?  THANKS.

  • Hey Tom,

    The VCOin voltage limitation is caused by the source follower circuit used to buffer the input voltage to the VCO in these CMOS logic-based PLLs.

    The datasheet for the newest version, SN74LV4046A shows an input voltage range of 1.1V minimum to 1.9V (3.3V operation) or 3.2V (5V operation) to maintain appropriate linearity. You might be able to push a little beyond those values in some cases, but it's best to design the system to meet the limitations.

    The plot shown has R1 = R2, which isn't the only way to configure the device. You should be able to configure it to get what you need.

    To determine the frequency range of the VCO, the app note you linked (SCHA003B: CMOS Phase-Locked-Loop Applications Using the CD54/74HC/HCT4046A and CD54/74HC/HCT7046A, pg 30) lists a useful set of equations.

    To get the minimum frequency, 

    fmin = Ka/(R2*C1)

    To get the maximum frequency,

    fmax = Ka/(Req*C1)

    To get the ratio of the two, we can divide fmax by fmin, and we get:

    fmax/fmin = R2/Req

    Req = R1*R2/(R1+R2), so we can further simplify:

    fmax_fmin = R2/( R1*R2 / (R1+R2) ) = ( R1+R2 ) / (R1) = 1+R2/R1

    It seems that if R2/R1 is larger than 15, then you should be able to get a ratio of 16.

    The 'quick calculations' section does go on to say that it's not quite that simple -- but this is a good starting point.

    Another note in the text mentions that leaving R2 open can produce instability when the input voltage gets below the minimum input voltage. You can add a resistor to R2 (for example, 300 kohm, the max listed in the VCO section) to avoid instability at the low-end of the frequency spectrum. That would limit the R1 value to 20kohm or smaller, based on the above calculation to keep a 16 ratio (or larger).

    Given all that info, I solved for frequency range of 12.8k to 204.8k (from above equations) and got:

    R2 = 300 kohm

    R1 = 18.8 kohm

    C1 = 2.2 nF

    I'd recommend starting there and tweaking R1/C1 values with a prototype build.

  • Thank you for this info.  I did purchase TI CD4046 and they work perfectly in my application.  They have a wider range ratio than I've experienced with the 74HC version.   Problem solved!

    Best,

    Tom

  • Hey Tom,

    That's great! I'm glad you were able to find a device that works for you.

    Feel free to come back if you run into any other snags in the future.