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CD4541B: Power on reset (necessity and gating)

Part Number: CD4541B

First question: am I correct that the state of the Q output is undefined at power-on if the chip is turned on with AR pulled HIGH?  And I will take it the state will stay undefined until a Manual Reset pulse is given in that case?  Or is the CD4541B's Q output guaranteed to power up in its inactive state if the chip is turned on with AR pulled HIGH?

Second (and thornier) question: is it feasible to use a reset-supervisor's output to "gate" the Auto Reset functionality of the CD4541B on during power-on, and off for the rest of the time? Is there some sort of minimum trigger voltage for the internal Auto Reset I need to be aware of? (I ask because I'm dealing with a battery powered app where an extra 30uA of current draw for a few seconds at powerup is far more acceptable than an extra 30uA of quiescent current draw)

  • With AUTO RESET disabled, the initial state is undefined.

    The datasheet implies that the auto reset triggers with the supply near 5 V.

  • The thing with that "near 5V" trigger threshold for the Auto Reset is that it's a typical value, and while the upper bound on that threshold is 8.5V, there's no lower bound specified.

  • Hey Lucas,

    I couldn't find mention of an 8.5V threshold in the CD4541B datasheet -- it does say "For reliable automatic power-on reset, VDD should be greater than 5V."

    This device can be operated at 3V also, so I'm sure that's the reason it was mentioned that at least 5V supply was required for reliable operation of the Power-on Reset (POR) circuit.

    There's no guarantee that the device will have a known state if the POR circuit is disabled.

  • Ah, I had my datasheets mixed up -- 8.5V is from the Nexperia datasheet for their version of the 4541; I suspect that number might be in error, even, as it doesn't make sense for a minimum for that value.  I think that I'll be going with my plans to use a reset supervisor to "strobe" the AR pin on power on, then.