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SN74AXC1T45: JTAG Pull-ups after level shifting

AI31
Expert 1600 points
Part Number: SN74AXC1T45

I'm using SN74A*** level shifters to level shift a 1.8V JTAG CPU to work with 3.3V debugger.

The question relates to JTAG Pull up/dn and termination resistors (mot shown on the schematic):

  • Where should I add the PU/DN resistors; at the 3V3 nets or the 1V8 ones?
  • Same as the 33Ohm series resistos if needed?

thanks

  • 0
    TI__Guru* 96591 points

    Hi Ahmed,

    What is the purpose of the pull-up / pull-down resistors?  Do you expect to have floating inputs?

    If so, place the appropriate (PU or PD) resistor on the wire that will not be defined.  You may need to do this on both sides if you have changing directions and the possibility of floating nodes on both sides of the device.  With JTAG this typically would not be the case though, since it is (as far as I know) a unidirectional protocol.

  • 0
    Guru 244360 points

    When the JTAG connector is unplugged, JTAG_1_TDO_3V3 is floating, so you need a pull-up/-down there.

    As far as I can see, the level shifter is never disabled or powered off. You would need pull-ups/-downs at the three 1.8 V outputs of the FPGA if they can be disabled at any time.

  • 0 in reply to Clemens Ladisch
    Expert 1600 points

    Hi Clemens and Emrys, 

    I recommend watching this video to know more about JTAG board requirements as per JTAG spec.

    www.youtube.com/watch

    I think all terminations should be on the 1V8 side except for TDO as Clemens said.

    One more thing is the TCLK, do you agree it should be on both sides? since the aim is to suppress reflections?

  • 0 in reply to AI31
    TI__Guru* 96591 points

    Hi Ahmed,

    The aim is to maintain a valid input signal when the input is not driven - the pull-up and pull-down resistors have nothing to do with reflection. It's up to you to know which signals in your system need this. If you have an issue with the JTAG specification, I'm afraid that TI has no control over that.