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SN74LV08A

hj
Intellectual 650 points
Other Parts Discussed in Thread: SN74LV08A, SN74LS07

I am using the AND gate SN74LV08A and 1Y was exposed to 11.5V while VCC was 3.3V. Could this harm the chip in any way?

Thanks in advance

  • 0
    TI__Genius 9860 points
    Hi hj, yes, this can harm the chip. There is an ESD diode from GND to the output that can experience reverse breakdown at voltages this high.

    You may still see normal operation of the chip, but TI cannot guarantee functionality once it has been exposed to beyond-absolute-maximum conditions.

    -Ryan
  • 0 in reply to C. Ryan Land
    Intellectual 650 points
    Thanks Ryan,

    Would it also be harmful for 1A or 1B to be exposed to the same voltage? And there is no way to predict functionality?
  • 0 in reply to hj
    TI__Genius 9860 points
    Yes, it would be harmful for 1A or 1B to be exposed to 11.5 V. See the Absolute Maximum Rating on page 4. We specify a stress limit of 7 V for Input Voltage Range.

    We guarantee datasheet electrical characteristics and performance when you are within Recommended Operating Conditions.
    We guarantee functionality (the device will behave like an AND gate) between Recommended and Absolute Maximum, but we don't guarantee any specific performance parameters.
    We do not guarantee functionality at all beyond Absolute Maximum.

    In many cases, the IC itself may be fine, but the user assumes all risk of failure if the device is exposed to beyond Abs Max.
  • 0 in reply to C. Ryan Land
    Intellectual 650 points
    Thank you,

    Do you know if TI supplies a similar part with a higher voltage rating? Possibly 12V?
    I still plan to use it at 3.3V logic. However, if the user accidentally attaches their device on a wrong channel, I would like to have protecting from that.
  • 0 in reply to hj
    TI__Genius 9860 points
    You could use two SN74LS07 devices and wire their corresponding outputs to the same pullup resistor in a wired-AND configuration. These devices can support up to 30 V on the output, and they are the only devices we have that can support that on the output. They can also output the 3.3-V logic levels since they're open drain. Their VOL levels may be a bit too high, though, for 3.3-V CMOS logic levels, and their VCC is in the 5V range.

    Alternatively, you could use an external Zener diode to limit the voltage that the output pin would be exposed to.

    -Ryan
  • 0 in reply to C. Ryan Land
    TI__Genius 9860 points
    Actually those VOL ranges might be compatible with most 3.3-V CMOS logic.
  • 0 in reply to C. Ryan Land
    Intellectual 650 points


    Currently we are seeing an offset on the output 1Y When the inputs of the gate are 0 as shown below. Do you have any suggestions how we can get the output as close to 0 as possible?

    Would a pull down resistor help lower the voltage to less than .5V? Thanks

    Vcc = 3.3V

    IN:1A 3.3V
    IN:1B 0V
    OUT:1Y 1.6V


    IN:1A 3.3V
    IN:1B 3.3V
    OUT:1Y 3.3V