Other Parts Discussed in Thread: SN74LV367A
Customer is using CD74HC4050 in a scenario where its VCC is turned off, but the logic on the load side of the buffer is not powered down (VCC = 5V). There is a pull-up resistor to VCC on the output load as well. There is excessive current being drawn by the unpowered CD74HC4050 buffer.
The current is probably due to the unpowered buffer getting powered up by the output through its ESD diodes as these parts do no have a partial power down protection built in. There is an old App Note that talks about methods to handle partial power down in HC and AC device (https://www.ti.com/lit/an/scla008/scla008.pdf).
One suggestion in the App Note is to place a diode between the VCC pin and its VCC source on the unpowered device, somewhat similar to the approach for built in Ioff features. (See Figure 5 of the App Note). I can see how this approach blocks current flow from the output to the unpowered VCC supply, but I don't think this would prevent the unpowered device from being powered up by the output voltage since there is still a path to the internal VCC rail through the output ESD diode.
Is this assumption correct? Other suggestions to allow partial power down with this device? .
