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SN74LVC1G126: Problem: The simulation results of thi-state gate are not correct, the result about high resistance state are same with an AND gate.

Part Number: SN74LVC1G126
Other Parts Discussed in Thread: SN74LVC1G125, SN74LVC1G17, SN74LVC1G32, SN74LVC1G08, SN74LVC1G02, SN74LVC1G00, SN74LVC1G14, SN74LVC1G04, TINA-TI, SN74HC125, SN74LVC1G18, SN74LVC1G66, SN74LVC1G79, SN74LVC1G175, SN74LVC1G373, SN74LVC1G374, SN74LVC1G3157

Problem: The simulation results of thi-state gate are not correct, the result about high resistance state are same with an AND gate.

In testing, Kicad and Ngspice are used as simulation platform, and the SPICE model of sn74lvc1g126 is downloaded from Ti Official Web and then renamed as sn74lvc1g126_TI_Official.txt. The sn74lvc1g126_SOT235_TI.lib, which is used for the thi-state gate model, is obtained by reordering pin's sequence.

I set the part symbol according to Fig 1. The error message is shown in Fig 2 when I run the simulator for the first time. I checked the official spice file and found that there seems to be a problem in two places, as shown in Fig 3. Then I tried to modify the data, change 3 to 3.6, as shown in Fig 4, and then ran the simulator to get the result as shown in Fig 5. However, this result is not correct. This is the result of AND gate, not result of high resistance state, which should be a horizontal line with a value of 4.5V.

The same problem also appeared in the simulation experiment for sn74lvc1g125 with official spice file. I don't know where the problem is. I guess there may be three possibilities:

1. There may be some errors in the TI official spice file.

2. There are some compatibility problems among the TI official spice files, KiCad and Ngspice.

3. I didn't use the simulation platform and official spice file in correct way. However, the TI official spice files such as sn74lvc1g00, sn74lvc1g02, sn74lvc1g04, sn74lvc1g08, sn74lvc1g14, sn74lvc1g17, sn74lvc1g32 were tested by the same method, and the correct results were obtained.

So, I want to know where is the simulation problem of sn74lvc1g126 or sn74lvc1g125 and hope to get your help, Thank you!

  • Hi,

    I'll take a look at this. Have you tried simulating the circuit in TINA-TI to see if it generates the same result?

    Thanks!

    Chad Crosby

  • Hello,

    I repeated the test with Tina Ti, and the result was the same. If there is nothing wrong with my operation, now I am even more suspicious that if there exist some problem in the official Pspice file for this part: the most important high resistance state of a thi-state gate does not seem to be implemented correctly.

    I'd like to hear from you。Thanks!

    Nu   ^_^

  • Hi,

    Let me take some time and get back to you on this.

    Thanks!

    Chad Crosby

  • Hi,

    I've found the fix. I'll work on fixing the model on the web, but in the meantime, you can fix it by doing the following:

    In your .cir file, search for the following line:
    .SUBCKT LOGIC_TRI_STATE_OUTPUT_HC_1i_AND_Tristate_CMOS_SN74HC125 IN OUT OEZ VCC VEE

    In this subcircuit, comment out LOUT

    This should leave only the transconductance (which switches to 0 once OE is toggled)

    Thanks!

    Chad Crosby

  • OK, the problem has been found and hope I can download the updated PSPICE file on the official product page soon. Please do not forget that the PSPICE model of SN74LVC1G125 has the same problem, which needs to be corrected.

    SN74LVC1Gxxx series of logic gate components are very fundamental in the simulation and verification for digital circuits. I am glad to see that TI company provides the so-called behavioral PSPICE model for most of them. However, the following components only provide HSPICE or IBIS models, it seems that Tina-Ti cannot use them. Therefore, even simple circuit simulation related to these components can not be completed at present.

    SN74LVC1G18 - Single Demutiplexer
    SN74LVC1G66 - Single Bilateral Analog Switch
    SN74LVC1G79 - Single D Flip-Flop
    SN74LVC1G175 - Single D Flip-Flop with Asynchronus Clear
    SN74LVC1G373 - Single D Latch Tri-State Output
    SN74LVC1G374 - Single D Flip-Flop Tri-State Output
    SN74LVC1G3157 - SPDT Analog Switch

    I don't know why. If there are no technical difficulties, I strongly recommend that TI can provide the Behavioral PSPICE models which support Tina-TI for these components, and hope you can feedback this desire to the related department of the company. thanks!

    Nu   ^_^

  • Hi,

    To keep it short, D-Flip Flops, or any state-machine related models, are difficult to model in Spice. Spice was created to model analog circuits, and can be a bit finicky when trying to make it model digital circuits.

    Once I can find a way to reliably create these D-Flip Flop models I'll work on getting them on the web, but it's going to take a while.

    I'm actually surprised to see that the SN74LVC1G18 doesn't have a model though, I'll work on getting that on the web.

    If you don't have any other questions, could you mark this thread as resolved? That'd really help me out.

    Thanks!

    Chad Crosby

  • Hello, Chad

    Since it's the first time I use this TI Technology Forum, I don't know the "resolved" green button must be clicked afterwards (T_T)... Anyway, thank you very much for your enthusiasm and work. I'll ask you for advise again if I meet any problems in the future.

    Sincerely

    Nu   ^_^

  • At the end of a week travel outside , I remembered that something had not been done, so according to  suggestion by TI engineer Chad Crosby:

    Delete the line of "LOUT" in a subcircuit (Highlighted) in PSPICE file.

    Simulation again, this time the results seems right.

    By the way, if the simulator is ngspice instead of Tina-TI or LTSpice, double "3v" problems still need to be modified.

    If the pull-up resistor select 1K instead of 100k, the output level of high resistance state will be very close to 5V